Wire bonding power interconnection

Proceedings - 2008 2nd Electronics Systemintegration Technology Conference, ESTC

Volumn , Issue , 2008, Pages 383-386

  Novotný, Marek ^a   Jankovsky, Jaroslav ^a   Szendiuch, Ivan ^a   Barton, Zdenek ^b  

^a BRNO UNIVERSITY OF TECHNOLOGY   (Czech Republic)

^b CEDO Ltd   (Czech Republic)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CONDUCTIVITY; ELECTRONIC EQUIPMENT MANUFACTURE; INTEGRATED CIRCUITS; NETWORKS (CIRCUITS); PRINTED CIRCUIT BOARDS; PRINTED CIRCUIT MANUFACTURE; RELIABILITY; SEMICONDUCTOR MATERIALS; STRESS CONCENTRATION;

CURRENT DISTRIBUTIONS; FINITE-ELEMENT MODELING; HIGH CURRENTS; REAL EXPERIMENTS; RECENT DEVELOPMENTS; SEMICONDUCTOR CHIPS; STRESS DISTRIBUTIONS; TEST SYSTEMS; VISCO PLASTICS; WIRE BONDINGS;

WIRE;

EID: 58149102006     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESTC.2008.4684379     Document Type: Conference Paper

References (4)

1. HARMAN, G., Wire Bonding in Microelectronics: Materials, Processes, Reliability, and Yield, McGraw-Hill (USA, 1997), pp. 212-213.
2. CAERS, J. F. J. M., BISCHOFF, A., FALK, J., & ROGGEN, J., "Conditions for reliable Ball-Wedge Copper Wire Bonding," Japan International ElectronicsManufacturing Technology Symposium, 1993, pp.312-315.
3. J. JANKOVSKY, M. NOVOTNY, I. SZENDIUCH. Design of Test Chip, Brno University of Technology, FEEC, Dept. of Microelectronic, 2006
4. J. JANKOVSKY, M. NOVOTNY, I. SZENDIUCH. Experimental Research on Power Packaging, Brno University of Technology, FEEC, Dept. of Microelectronic, 2006