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Volumn , Issue , 2008, Pages

Machine-code verification for multiple architectures: An application of decompilation into logic

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; DIGITAL SIGNAL PROCESSING; LINGUISTICS; SPECIFICATIONS;

EID: 58049135249     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FMCAD.2008.ECP.24     Document Type: Conference Paper
Times cited : (58)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.