A 211 GOPS/W dual-mode real-time object recognition processor with network-on-chip

ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference

Volumn , Issue , 2008, Pages 462-465

  Kim, Kwanho ^a   Kim, Joo Young ^a   Lee, Seungjin ^a   Kim, Minsu ^a   Yoo, Hoi Jun ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK TOPOLOGY; ELECTRIC POWER UTILIZATION; ENERGY MANAGEMENT; VERY LONG INSTRUCTION WORD ARCHITECTURE;

CHIP INTEGRATES; CMOS PROCESSES; DUAL MODES; LOW POWERS; NETWORK ON CHIPS; PEAK PERFORMANCES; POWER CONSUMPTIONS; POWER MANAGEMENT SCHEMES; PROCESSING ELEMENTS;

OBJECT RECOGNITION;

EID: 58049103652     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2008.4681892     Document Type: Conference Paper

References (7)

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