Stress enhancement concept on replacement gate technology with top-cut stress liner for nFETs

ESSDERC 2008 - Proceedings of the 38th European Solid-State Device Research Conference

Volumn , Issue , 2008, Pages 174-177

  Yamakawa, S ^a   Mayuzumi, S ^a   Tateshita, Y ^a   Wakabayashi, H ^a   Ansai, H ^a  

^a SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON MOBILITY; MOSFET DEVICES;

BAND MODELS; CHANNEL REGIONS; DUMMY GATES; GATE LENGTHS; LATERAL STRESSES; MOBILITY ENHANCEMENTS; REPLACEMENT GATES; STRESS ENHANCEMENTS; TENSILE STRESS LINERS;

TENSILE STRENGTH;

EID: 58049096040     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2008.4681727     Document Type: Conference Paper

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