The AES in a systolic fashion: Implementation and results of celator processor

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

Volumn , Issue , 2008, Pages 380-383

  Fronte, Daniele ^a   Perez, Annie ^a   Payrat, Eric ^b  

^a AIX MARSEILLE UNIVERSITÉ   (France)

^b Atmel   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ARM PROCESSORS; COMPUTER ARCHITECTURE; DATA PRIVACY; DATA TRANSFER; GENERAL PURPOSE COMPUTERS; HARDWARE SECURITY; PROGRAM PROCESSORS; RANDOM ACCESS STORAGE; RECONFIGURABLE HARDWARE; SYSTOLIC ARRAYS;

ADVANCED ENCRYPTION STANDARD; GENERAL PURPOSE PROCESSORS; INTERFACE UNITS; PERFORMANCE COMPARISON; PROCESSING ELEMENTS; RE-CONFIGURABILITY; RECONFIGURABLE CIRCUITS; SYSTEM ARCHITECTURES;

CRYPTOGRAPHY;

EID: 57849133679     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2008.4674870     Document Type: Conference Paper

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