Ultra-scaled Z-RAM cell

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2008, Pages 157-158

  Okhonin, S ^a   Nagoga, M ^a   Lee, C W ^b   Colinge, J P ^b   Afzalian, A ^b   Yan, R ^b   Dehdashti Akhavan, N ^b   Xiong, W ^c   Sverdlov, V ^d   Selberherr, S ^d   Mazure, C ^e  

^a PSE B   (Switzerland)

^b UNIVERSITY COLLEGE CORK   (Ireland)

^c TEXAS INSTRUMENTS   (United States)

^d VIENNA UNIVERSITY OF TECHNOLOGY   (Austria)

^e PARC TECHNOLOGIQUE DES FONTAINES   (France)

Author keywords

[No Author keywords available]

Indexed keywords

TRANSIENT ANALYSIS;

AND GATES; CELL PERFORMANCES; CHANNEL DOPING; FIN WIDTHS; GATE LENGTHS; OPERATIONAL PRINCIPLES; PHYSICAL PARAMETERS; TRANSIENT MEASUREMENTS;

RANDOM ACCESS STORAGE;

EID: 57749199319     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOI.2008.4656342     Document Type: Conference Paper

References (5)

1. J.-P. Colinge, "FinFETs and Other Multi-Gate Transistors", Springer, 2007, p. 18.
2. S. Okhonin et al, IEDM, 2007, pp. 925-928.
3. I. Ban et al, VLSI Symp., 2008, pp. 92-93.
4. F. Matsuoka et al, IEDM, 2007, pp. 39-42.
5. C. W. Oh et al, VLSI Symp., 2007, pp. 168-169.