Capping-metal gate integration technology for multiple-VT CMOS in MuGFETs

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2008, Pages 119-120

  Veloso, A ^a   Witters, L ^a   Demand, M ^a   Ferain, I ^c   Son, N J ^b   Kaczer, B ^a   Roussel, Ph J ^a   Adelmann, C ^a   Brus, S ^a   Richard, O ^a   Bender, H ^a   Conard, T ^a   Vos, R ^a   Rooyackers, R ^a   Van Elshocht, S ^a   Collaert, N ^a   De Meyer, K ^c   Biesemans, S ^a   Jurczak, M ^a  

^a IMEC ^*

^b IMEC   (Belgium)

^c UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 57749194404     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOI.2008.4656323     Document Type: Conference Paper

References (7)

1. V. Narayanan et al., VLSI Tech. Dig. 2006, 224;
2. T. Lee et al., EDL 27(8), 640 (2006);
3. H.-S. Jung et al., VLSI Tech. Dig. 2006, 204;
4. H.-S. Jung et al., VLSI Tech. Dig. 2007, 196;
5. A. Veloso et al., VLSI2008 (accepted);
6. N. Collaert et al., VLSI Tech. Dig. 2005, 108;
7. B. Kaczer et al., IRPS2008.