Voltage gain analysis of integrated Fibonacci-like charge pumps for low power applications

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 54, Issue 11, 2007, Pages 929-933

  Cabrini, Alessandro ^a   Gobbi, Laura ^a   Torelli, Guido ^a  

^a UNIVERSITY OF PAVIA   (Italy)

Author keywords

Charge pump; Fibonacci like; Network matrix; Voltage elevator; Voltage gain

Indexed keywords

CHARGE PUMP CIRCUITS; GAIN MEASUREMENT;

ANALYTICAL EXPRESSIONS; CHARGE PUMP; CIRCUIT-LEVEL SIMULATION; FIBONACCI-LIKE; LOW POWER APPLICATION; NETWORK MATRICES; PARASITIC CAPACITANCE; VOLTAGE GAIN;

CAPACITANCE;

EID: 57549094990     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2007.904156     Document Type: Article

References (15)

1. J. F. Dickson, "On chip high voltage generation in Mnos integrated circuits using an improved voltage multiplier technique," IEEE J. Solid-State Circuits, vol. 11, no. 6, pp. 374-378, Jun. 1976.
2. P. Favrat, P. Deval, and M. Declerq, "A high-efficiency Cmos voltage doubler," IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 410-416, Mar. 1998.
3. J. Starzyk, Y.-W. Jan, and F. Qiu, "A dc-dc charge pump based on voltage doublers," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 48, no. 3, pp. 350-359, Mar. 2001.
4. G. Palumbo, D. Pappalardo, and M. Gaibotti, "Charge pumps circuits: Power consumption optimization," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 49, no. 11, pp. 1535-1542, Nov. 2002.
5. G. Palumbo and D. Pappalardo, "Charge pump circuits with only capacitive loads: Optimized design," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 53, no. 2, pp. 128-132, Feb. 2006.
6. M. Hoque, T. Ahmad, T. McNutt, H. Mantooth, and M. Mojarradi, "A technique to increase the efficiency of high-voltage charge pumps," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 53, no. 5, pp. 364-368, May 2006.
7. M. Ker and S. Chen, "Ultra-high-voltage charge pump circuit in low-voltage bulk cmos processes with polysilicon diodes," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 54, no. 1, pp. 47-51, Jan. 2007.
8. F. Ueno, T. Inoue, I. Oota, and I. Harada, "Emergency power supply for small computer systems," in Proc. IEEE Int. Symp. Circuits Syst., Jun. 1991, pp. 1065-1068.
9. M. Makowski, "Realizability conditions and bounds on synthesis of switched-capacitor dc-dc voltage multiplier circuits," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 44, no. 8, pp. 684-691, Aug. 1997.
10. M. D. Seeman and S. R. Sanders, "Analysis and optimization of switched-capacitor dc-dc converters," in Proc. IEEE Workshop Comput. Power Electron., May 2006, pp. 213-223.
11. T. Tanzawa and T. Tanaka, "A dynamic analysis of the Dickson charge pump circuit," IEEE J. Solid-State Circuits, vol. 32, no. 8, pp. 1231-1240, Aug. 1997.
12. L. Gobbi, A. Cabrini, and G. Torelli, "Impact of parasitic elements on Cmos charge pumps: A numerical analysis," in Proc. IEEE Int. Symp. Circuits Syst., May 2006, pp. 3125-3128.
13. Y. P. Tsividis, "Analysis of switched capacitive networks," IEEE Trans. Circuits Syst., vol. CAS-26, no. 11, pp. 935-947, Nov. 1979.
14. A. Umezawa, S. Atsumi, M. Kuriyama, H. Banba, K. Imamiya, K. Naruke, S. Yamada, E. Obi, M. Oshikiri, T. Suzuki, and S. Tanaka, "A 5 V -only operation 0.6-μm flash Eeprom with row decoder scheme in triple-well technology," IEEE J. Solid-State Circuits, vol. 27, no. 11, pp. 1540-1546, Nov. 1992.
15. G. Palumbo, N. Barniol, and M. Bethaoui, "Improved behavioural and design model of an nth order charge pump," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 47, no. 2, pp. 264-268, Feb. 2000.