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Volumn , Issue , 2008, Pages 919-920

An analyzer for extended compositional process algebras

Author keywords

Fairness; Model Checking; SAT Solvers; Simulation

Indexed keywords

ART MODELS; BOUNDED MODELS; DEADLOCK FREENESS; EVENT-BASED; FAIRNESS; FAIRNESS CONSTRAINTS; GLOBAL VARIABLES; INTERACTIVE SYSTEMS; MODEL CHECKERS; MODEL-CHECKING TECHNIQUES; NUMBER OF STATE; ON THE FLIES; PARAMETERIZED; PROCESS ALGEBRAS; REACHABILITY; SAT PROBLEMS; SAT SOLVERS; SIMULATION; SUPPORT SYSTEMS; SYSTEM MODELS; SYSTEM SIMULATIONS; USER-FRIENDLY INTERFACES; ART MODEL; BOUNDED MODEL; INTERACTIVE SYSTEM; LINEAR TEMPORAL LOGIC; MODEL CHECKER; ON-THE-FLY; USER FRIENDLY INTERFACE;

EID: 57349173969     PISSN: 02705257     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1370175.1370187     Document Type: Conference Paper
Times cited : (20)

References (5)
  • 5
    • 57349130244 scopus 로고    scopus 로고
    • J. Sun, Y. Liu, and J. S. Dong. A Simulator and Model Checker for Extended CSP. http://www.comp.nus.edu.sg/̃liuyang/pat/, 2008.
    • J. Sun, Y. Liu, and J. S. Dong. A Simulator and Model Checker for Extended CSP. http://www.comp.nus.edu.sg/̃liuyang/pat/, 2008.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.