Fabrication of 32nm contact/via hole by photolithographic-friendly method

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6923, Issue , 2008, Pages

  Kawasaki, Tetsu ^a   Shimura, Satoru ^a   Iwao, Fumiko ^a   Nishimura, Eiichi ^a   Kushibiki, Masato ^a   Hasebe, Kazuhide ^a   Carcasi, Michael ^b   Somervell, Mark ^b   Scheer, Steven ^b   Yaegashi, Hidetami ^a  

^a TOKYO ELECTRON LTD   (Japan)

^b TOKYO ELECTRON AMERICA INC   (United States)

Author keywords

32nm 22nm node contact hole; Double patterning; Hole shrink; Immersion lithography

Indexed keywords

ELECTRIC CONDUCTIVITY; PHOTOLITHOGRAPHY; SEMICONDUCTOR MATERIALS;

193NM IMMERSION LITHOGRAPHIES; 32NM/22NM NODE CONTACT HOLE; DOUBLE PATTERNING; EUV LITHOGRAPHIES; HOLE PATTERNS; HOLE SHRINK; IMMERSION LITHOGRAPHIES; IMMERSION LITHOGRAPHY; LITHOGRAPHY PROCESSES; MAJOR FACTORS; NODE GENERATIONS; PATTERN FORMATIONS; PRESENT STAGES; PROCESS MARGINS; PROCESSING TECHNOLOGIES; PRODUCTION COSTS; PRODUCTION PROCESSES; SEMICONDUCTOR DESIGNS; SEMICONDUCTOR LITHOGRAPHIES; SEMICONDUCTOR PRODUCTIONS; SHRINK PROCESSES; SHRINK TECHNOLOGIES; SPACE PATTERNS;

TECHNOLOGY;

EID: 57349168547     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.771907     Document Type: Conference Paper

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