JLS: A pedagogically targeted logic design and simulation tool

Proceedings of the Conference on Integrating Technology into Computer Science Education, ITiCSE

Volumn , Issue , 2008, Pages 314-

  Poplawski, David A ^a   Kurmas, Zachary ^b  

^a Michigan Technological University

^b GRAND VALLEY STATE UNIVERSITY   (United States)

Author keywords

Design

Indexed keywords

CIRCUIT DESIGNS; CLASSROOM PRESENTATIONS; COMMERCIAL PRODUCTS; COMPUTER ORGANIZATION COURSES; DESIGN AND SIMULATIONS; DIGITAL LOGICS; DRAWING INTERFACES; ERROR-CHECKING; SIMULATION RESULTS; TRUTH TABLES;

COMPUTERS; CURRICULA; DIGITAL ARITHMETIC; EDUCATION COMPUTING; INTEGRATED CIRCUIT MANUFACTURE; LOGIC CIRCUITS; LOGIC DESIGN; NETWORKS (CIRCUITS); SCHOOL BUILDINGS; SWITCHING THEORY; TOOLS;

INNOVATION;

EID: 57349156625     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1384271.1384357     Document Type: Conference Paper

References (0)