Improving student performance using automated testing of simulated digital logic circuits

Proceedings of the Conference on Integrating Technology into Computer Science Education, ITiCSE

Volumn , Issue , 2008, Pages 265-269

  Kurmas, Zachary ^a  

^a GRAND VALLEY STATE UNIVERSITY   (United States)

Author keywords

Digital logic; JLS; Simulation; Testing

Indexed keywords

AUTOMATIC EVALUATIONS; CIRCUIT UNDER TESTS; DIGITAL LOGIC; DIGITAL LOGIC CIRCUITS; DIGITAL LOGICS; JLS; OUTPUT VALUES; SIMULATION; STUDENT PERFORMANCES; TIME CONSUMING;

COMPUTER TESTING; COMPUTERS; DIGITAL ARITHMETIC; DIGITAL CIRCUITS; EDUCATION COMPUTING; INNOVATION; NETWORKS (CIRCUITS); SWITCHING CIRCUITS; SWITCHING THEORY;

LOGIC CIRCUITS;

EID: 57349135772     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1384271.1384342     Document Type: Conference Paper

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