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Volumn , Issue , 2008, Pages 185-187
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Brief announcement: Optimal speedup on a low-degree multi-core parallel architecture (LoPRAM)
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Author keywords
Algorithms; Theory
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Indexed keywords
ALGORITHMS;
ARCHITECTURE;
COMPUTER ARCHITECTURE;
MICROPROCESSOR CHIPS;
PARALLEL PROCESSING SYSTEMS;
RANDOM ACCESS STORAGE;
DESIGN AND ANALYSES;
HIGH LEVEL OF ABSTRACTIONS;
LOW DEGREES;
MICRO-PROCESSORS;
PARALLEL ARCHITECTURES;
PARALLEL PROGRAMS;
PRAM MODELS;
SEQUENTIAL ALGORITHMS;
SIMPLE MODIFICATIONS;
SPEED-UP;
THEORY;
PARALLEL ALGORITHMS;
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EID: 57349088105
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1145/1378533.1378568 Document Type: Conference Paper |
Times cited : (11)
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References (18)
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