An integrated memory array processor with a synchronous-DRAM interface for real-time vision applications

Proceedings - International Conference on Pattern Recognition

Volumn 4, Issue , 1996, Pages 575-580

  Yamashita, Nobuyuki ^a   Fujita, Yoshihiro ^a   Okazaki, Shin'Ichiro ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY IMAGES; DATA TRANSFER; FEATURE EXTRACTION; HOUGH TRANSFORMS; IMAGE ENHANCEMENT; MEMORY ARCHITECTURE; OBJECT RECOGNITION;

LINEAR PROCESSOR ARRAYS; LOW LEVEL IMAGE PROCESSING; MEMORY CAPACITY; PEAK PERFORMANCE; PROCESSING ELEMENTS; REAL TIME VISION; REAL-TIME IMAGE PROCESSING; SYNCHRONOUS DRAMS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 57049102953     PISSN: 10514651     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPR.1996.547630     Document Type: Conference Paper

References (8)

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8. S. Okazaki, et al., "A Compact Real-time Vision System Using Integrated Memory Array Processor Architecture, " IEEE Trans. on Circuits and Systems for Video Technology, Vol.5, No.5, pp.446-452, Oct., 1995.