Optimizing thread throughput for multithreaded workloads on memory constrained CMPs

Conference on Computing Frontiers - Proceedings of the 2008 Conference on Computing Frontiers, CF'08

Volumn , Issue , 2008, Pages 119-128

  Bhadauria, Major ^a   Mckee, Sally A ^a  

^a Cornell University ^*  (United States)

Author keywords

Bandwidth; Efficiency; Memory; Performance; Power

Indexed keywords

DYNAMIC RANDOM ACCESS STORAGE; TELECOMMUNICATION SYSTEMS;

AVERAGE ENERGIES; CORE DESIGNS; DRAM MEMORIES; L2 CACHES; MEMORY; MEMORY ACCESSES; MEMORY CONTROLLERS; MICROARCHITECTURAL DESIGNS; MULTITHREADED WORKLOADS; NUMBER OF THREADS; PERFORMANCE; POWER; POWER BUDGETS; SENSE AMPLIFIERS; SPATIAL LOCALITIES; SPEED-UP;

MICROPROCESSOR CHIPS;

EID: 56749097288     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1366230.1366256     Document Type: Conference Paper

References (28)

1. R. Balasubramonian, D. Albonesi, A. Buyuktosunoglu, and S. Dwarkadas. Dynamic memory hierarchy performance optimization. In Workshop on Solving the Memory Wall Problem, held at the 27th International Symposium on Computer Architecture, June 2000.
2. D. Burger, J. Goodman, and A. Kägi. Memory bandwidth limitations of future microprocessors. In Proc. 23rd IEEE/A CM International Symposium on Computer Architecture, pages 78-89, May 1996.
3. J. Carter, W. Hsieh, L. Stoller, M. Swanson, L. Zhang, E. Brunvand, A. Davis, C.-C. Kuo, R. Kuramkote, M. Parker, L. Schaelicke, and T. Tateyama. Impulse: Building a smarter memory controller. In Proc. Fifth Annual, Symposium on High Performance Computer Architecture, pages 70-79, Jan. 1999.
4. V. Cuppu, B. Jacob, B. Davis, and T. Mudge. A performance comparison of contemporary DRAM architectures. In Proc. 26th IEEE/ACM International Symposium on Computer Architecture, pages 222-233, May 1999.
5. M. Curtis-Maury, K. Singh, S. McKee, F. Blagojevic, D. Nikolopoulos, B. de Supinski, and Schulz. Identifying energy-efficient concurrency levels using machine learning. In Proc. 1st International Workshop on Green Computing, Sept. 2007.
6. B. Ganesh, A. Jaleel, D. Wang, and B. Jacob. Fully-buffered dimm memory architectures: Understanding mechanisms, overheads and scaling. In Proc. 13th IEEE Symposium, on High Performance Computer Architecture, pages 109-120, Feb. 2007.
7. H. Hidaka, Y. Matsuda, M. Asakura, and K. Fujishima. The cache dram architecture: A dram with an on-chip cache memory. IEEE Micro, 10(2): 14-25, 1990.
8. I. Hur and C. Lin. Adaptive history-based memory schedulers. In Proc. IEEE/ACM 38th Annual International Symposium, on Microarchitecture, pages 343-354, Dec. 2004.
9. B. Jacob. A case for studying DRAM issues at the system level. IEEE Micro, 23(4):44-56, 2003.
10. A. Jaleel. The effects of aggressive out-of-order mechanisms on the memory sub-system. Ph.D. dissertation, University of Maryland, July 2005.
11. A. Jaleel and B. Jacob. Using virtual load/store queues (vlsqs) to reduce the negative effects of reordered memory instructions. In Proc. 11th IEEE Symposium on High Performance Computer-Architecture, pages 266-277, Feb. 2005.
12. N. Kim, T. Austin, D. Baauw, T. Mudge, K. Flautner, J. Hu, M. Irwin, M. Kandemir, and V. Narayanan. Leakage current: Moore's law meets static power. IEEE Computer, 36(12):68-75, Dec. 2003.
13. T. Kirihata, G. Mueller, B. Ji, G. Frankowsky, J. Ross, H. Terletzki, D. Netis, O. Weinfurtner, D. Hanson, G. Daniel, L.-C. Hsu, D. Sotraska, A. Reith, M. Hug, K. Guay, M. Selz, P. Poechmueller, H. Hoenigschmid, and M. Wordeman. A 390-mm2, 16-bank, 1-gb ddr sdram with hybrid bitlinearchitecture. IEEE Journal of Solid-State Circuits, 34(11):1580-1588, 1999.
14. N. Kirman, M. Kirman, R. Dokania, J. Martinez, A. Apsel, M. Watkins, and D. Albonesi. Leveraging optical technology in future bus-based chip multiprocessors. In Proc. IEEE/ACM 40th Annual International Symposium, on Microarchitecture, pages 492-503, Dec. 2006.
15. W. Lin, S. Reinhardt, and D. Burger. Reducing DRAM latencies with an integrated memory hierarchy design. In Proc. 7th IEEE Symposium on High Performance Computer Architecture, pages 301-312, Jan. 2001.
16. S. McKee, W. Wulf, J. Aylor, R. Klenke, M. Salinas, S. Hong, and D. Weikle. Dynamic access ordering for streamed computations. IEEE Transactions on Computers, 49(11):1255-1271, Nov. 2000.
17. K. Nesbit, N. Aggarwal, J. Laudon, and J. Smith. Fair queuing memory systems. In Proc. IEEE/ACM 40th Annual International Symposium, on Microarchitecture, pages 208-222, Dec, 2006.
18. J. Renau. SESC. http://sesc.sourceforge.net/index.html, 2002.
19. S. Rixner, W. Dally, U. Kapasi, P. Mattson, and J. Owens. Memory access scheduling. In Proc. 27th IEEE/A CM International Symposium on Computer Architecture, pages 128-138, June 2000.
20. R. Sites. It's the Memory, Stupid! Microprocessor-Report, 10(10):2-3, Aug. 1006.
21. M. Stan and K. Skadron. Guest editors' introduction: Power-aware computing. IEEE Computer, 36(12):35-38, Dec. 2003.
22. Standard Performance Evaluation Corporation. SPEC OMP benchmark suite. http://www.specbench.org/hpg/omp2001/, 2001.
23. D. Wang, B. Ganesh, N. Tuaycharoen, K. Baynes, A. Jaleel, and B. Jacob. DRAMsim: A memory-system simulator. In Computer Architecture News, volume 33, pages 100-107, Sept. 2005.
24. D. T. Wang. Modern dram memory systems: Performance analysis and a high performance, power-constrained dram-scheduling algorithm. Ph.D. dissertation, University of Maryland, May 2005.
25. S. Woo, M. Ohara, E. Torrie, J. Singh, and A. Gupta. The SPLASH-2 programs: Characterization and methodological considerations. In Proc. 22nd IEEE/A CM International Symposium on Computer Architecture, pages 24-36, June 1995.
26. W. Wulf and S. McKee. Hitting the wall: Implications of the obvious. Computer Architecture News, 23(1):20-24, Mar. 1995.
27. T. Yamauchi, L. Hammond, and K. Olukotun. The hierarchical multi-bank dram: A high-performance architecture for memory integrated with processors. In Conference on Advanced Research in VLSI, pages 303-320, Nov. 1997.
28. Z. Zhang, Z. Zhu, and X. Zhang. Cached DRAM for ILP processor memory access latency reduction. IEEE Micro, 21(4):22-32, July/August 2001.