Simultaneous optimization of memory configuration and code allocation for low power embedded systems

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2008, Pages 403-406

  Matsumura, Tadayuki ^a   Ishihara, Tohru ^a   Yasuura, Hiroto ^a  

^a KYUSHU UNIVERSITY   (Japan)

Author keywords

Code allocation; Low power design; On chip memory

Indexed keywords

ACCESS DELAYS; AREA OVERHEADS; CODE ALLOCATION; DYNAMIC POWERS; HYBRID MEMORIES; LOW POWER DESIGN; LOW POWERS; MEMORY ACCESS DELAYS; MEMORY ARRAYS; MEMORY CONFIGURATIONS; ON-CHIP MEMORY; OPTIMIZATION PROBLEMS; SIMULTANEOUS OPTIMIZATIONS; STATIC NOISE MARGINS; STATIC POWERS; TOTAL POWER CONSUMPTIONS;

COMMUNICATION CHANNELS (INFORMATION THEORY); ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRIC POWER UTILIZATION; IMAGE CODING; INTEGRATED CIRCUITS; LAKES; OPTIMIZATION; RADIOACTIVE MATERIALS;

EMBEDDED SYSTEMS;

EID: 56749090645     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1366110.1366206     Document Type: Conference Paper

References (8)

1. H. Chang and Sachin S. Sapatnekar "Full-Chip Analysis of Leakage Power Under Process Variations, Including Spatial Correlations", in Proc. of DAC, pp.523-528, June, 2005.
2. S. Segars, "Low Power Design Techniques for Microprocessors", ISSCC Tutorial note, Feb. 2001.
3. S. Stenke, L. Whmeryer, B. Lee and P. Marwedl, "Assigning Program and Data Objects to Scratched for Energy Reduction" in Proc of Design, Automation and Test in Europe Conference and Exhibition, pp.409-415, 2002.
4. R. Banakar, S. Steinko, B. Lee, M. Balakrishnan and P. Marwedel, "Scratchpad Memory:A Design Alternative for Cache On-chip memory in Embedded Systems" in Prof of Design space exploration and architectural design of HW/SW system, pp73-78, 2002.
5. A. Sakanaka, S.Fujii and T. Sato, "A Leakage-Energy-Reduction Technique for Highly-Associative Cache in Embedded Systems" ACM SIGARCH Computer Architecture News Vol. 32, No. 3, June 2004.
6. Naoyuki Kawabe and Kimiyoshi Usami, "Low-Power Technique for On-Chip Memory Using Biased Partitioning and Access Concentration" IEEE Custom Integrated Circuits Conference, pp. 275-278, May. 2000.
7. T. Ishihara and K. Asada, "A System Level Power Optimization Technique Using Multiple Supply and Threshold Voltages", in Proc. of ASP-DAC, pp.456-461, 2001
8. E. Seevinck, F. List, and J. Lohstoh, "Static-Noise margin analysis of MOS SRAM cells" IEEE J. Solid-State Circuits, vol. SC-22, pp.748-754, 1987.