MOSFET degradation under RF stress

IEEE Transactions on Electron Devices

Volumn 55, Issue 11, 2008, Pages 3167-3174

  Sasse, Guido T ^a   Kuper, Fred G ^a,b   Schmitz, Jurriaan ^b  

^a NXP SEMICONDUCTORS   (Netherlands)

^b UNIVERSITY OF TWENTE   (Netherlands)

Author keywords

Breakdown; CMOS; Device reliability; Dielectric breakdown; Dielectrics; Hot carrier degradation; Negative bias temperature instability (NBTI); Reliability; RF; RF CMOS

Indexed keywords

CIVIL AVIATION; DEGRADATION; DIELECTRIC MATERIALS; ELECTRIC BREAKDOWN; GATE DIELECTRICS; GATES (TRANSISTOR); NETWORKS (CIRCUITS); RELIABILITY; TRANSISTOR TRANSISTOR LOGIC CIRCUITS; TRANSISTORS;

BREAKDOWN; CMOS; DEVICE RELIABILITY; DIELECTRIC BREAKDOWN; DIELECTRICS; HOT-CARRIER DEGRADATION; NEGATIVE-BIAS TEMPERATURE INSTABILITY (NBTI); RF; RF CMOS;

MOSFET DEVICES;

EID: 56549109662     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2008.2004650     Document Type: Article

References (42)

1. C. Hu, "Reliability phenomena under AC stress," Microelectron. Reliab., vol. 38, no. 1, pp. 1-5, Feb. 1998.
2. G. T. Sasse, R. J. de Vries, and J. Schmitz, "Methodology for performing RE reliability experiments on a generic test structure," in Proc. Int. Conf. Microelectron. Test Struct., 2007, pp. 177-182.
3. G. T. Sasse and J. Schmitz, "Application and evaluation of the RF charge-pumping technique," IEEE Trans. Electron Devices, vol. 55, no. 3, pp. 881-889, Mar. 2008.
4. L. Larcher, D. Sanzogni, R. Brama, A. Mazzanti, and F. Svelto, "Oxide breakdown after RE stress: Experimental analysis and effects on power amplifier operation," in Proc. Int. Rel. Phys. Symp., 2006, pp. 283-288.
5. A. Acovic, G. La Rosa, and Y.-C. Sun, "A review of hot-carrier degradation mechanisms in MOSFETs," Microelectron. Reliab., vol. 36, no. 7/8, pp. 845-869, Jul./Aug. 1996.
6. G. Groeseneken, R. Degraeve, T. Nigam, G. Van den Bosch, and H. E. Maes, "Hot carrier degradation and time-dependent dielectric breakdown in oxides," Microelectron. Eng., vol. 49, no. 1, pp. 27-40, Nov. 1999.
7. S.-G. Lee, J.-M. Hwang, and H.-D. Lee, "Experimental evidence for nonlucky electron model effect in 0.15-μm NMOSFETs," IEEE Trans. Electron Devices, vol. 49, no. 11, pp. 1876-1881, Nov. 2002.
8. P. Habas, "Hot-carrier aging of nMOST in analog circuits with large periodic drain signal," Solid State Electron., vol. 50, no. 5, pp. 727-732, May 2006.
9. K. R. Mistry and B. Doyle, "AC versus DC hot-carrier degradation in n-channel MOSFETs," IEEE Trans. Electron Devices, vol. 40, no. 1, pp. 96-104, Jan. 1993.
10. R. Bellens, P. Heremans, G. Groeseneken, H. E. Maes, and W. Weber, "The influence of the measurement setup on enhanced AC hot carrier degradation of MOSFETs," IEEE Trans. Electron Devices, vol. 37, no. 1, pp. 310-313, Jan. 1990.
11. E. S. Snyder, D. V. Campbell, S. E. Swanson, and D. G. Pierce, "Novel self-stressing test structures for realistic high-frequency reliability characterization," in Proc. Int. Rel. Phys. Symp., 1993, pp. 57-65.
12. V.-H. Chan, T. E. Kopley, P. Marcoux, and J. E. Chung, "High-frequency AC hot-carrier degradation in CMOS circuits," in IEDM Tech. Dig., 1994, pp. 299-302.
13. C. Jiang and E. Johnson, "AC hot-carrier degradation in a voltage controlled oscillator," in Proc. Int. Rel. Phys. Symp., 1993, pp. 53-56.
14. S. Yoshida, T. Matsui, K. Okuyama, and K. Kubota, "AC hot-carrier degradation in the super- 100 MHz operation range," in VLSI Symp. Tech. Dig., 1994, pp. 145-146.
15. C. D. Presti, F. Carrara, A. Scuderi, S. Lombardo, and G. Palmisano, "Degradation mechanisms in CMOS power amplifiers subject to radiofrequency stress and comparison to the DC case," in Proc. Int. Rel. Phys. Symp., 2007, pp. 86-92.
16. M. Tsuno, M. Suga, M. Tanaka, K. Shibahara, M. Miura-Mattausch, and M. Hirose, "Physically-based threshold voltage determination for MOSFETs of all gate lengths," IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1429-1434, Jul. 1999.
17. T. Grasser and S. Selberherr, "Special Section: Modelling the negative bias temperature instability," Microelectron. Reliab., vol. 46, no. 6, pp. 839-911, 2007.
18. V. Huard, M. Denais, and C. Parthasarathy, "NBTI degradation: From physical mechanisms to modelling," Microelectron. Reliab., vol. 46, no. 1, pp. 1-23, Jan. 2006.
19. M. A. Alain, H. Kufluoglu, D. Varghese, and S. Mahapatra, "A comprehensive model for pMOS NBTI degradation: Recent progress," Microelectron. Reliab., vol. 47, no. 6, pp. 853-862, Jun. 2007.
20. D. K. Schroder, "Negative bias temperature instability: What do we understand?" Microelectron. Reliab., vol. 47, no. 6, pp. 841-852, Jun. 2007.
21. B. Zhu, J. S. Suehle, Y. Chen, and J. B. Bernstein, "Negative bias temperature instability of deep sub-micron p-MOSFETs under pulsed bias stress," in Proc. Integr. Rel. Workshop Final Rep., 2002, pp. 125-129.
22. W. Abadeer and W. Ellis, "Behavior of NBTI under AC dynamic circuit conditions," in Proc. Int. Rel. Phys. Symp., 2003, pp. 17-22.
23. S. Mahapatra, M. A. Alam, P. Bharath Kumar, T. R. Dalei, and D. Saba, "Mechanism of negative bias temperature instability in CMOS devices: Degradation, recovery and impact of nitrogen," in IEDM Tech. Dig. 2004, pp. 105-108.
24. A. T. Krishnan, C. Chancellor, S. Chakravarthi, P. E. Nicollian, V. Reddy, A. Varghese, R. B. Khamankar, and S. Krishnan, "Material dependence of hydrogen diffusion: Implications for NBTI degradation," in IEDM Tech. Dig., 2005, pp. 688-691.
25. S. S. Tan, T. P. Chen, and L. Chan, "Dynamic NBTI lifetime model for inverter-like waveform," Microelectron. Reliab., vol. 45, no. 7/8, pp. 1115-1118, Jul./Aug. 2005.
26. T. Nigam and E. B. Harris, "Lifetime enhancement under high frequency NBTI measured on ring oscillators," in Proc. Int. Rel. Phys. Symp. 2006, pp. 289-293.
27. V. Huard and M. Denais, "Hole trapping effect on methodology for DC and AC negative bias temperature instability measurements in pMOS transistors," in Proc. Int. Rel. Phys. Symp., 2004, pp. 40-45.
28. G. Chen, M. F. Li, C. H. Ang, J. Z. Zheng, and D. L. Kwong, "Dynamic NBTI of p-MOS transistors and its impact on MOSFET scaling," IEEE Electron Device Lett., vol. 23, no. 12, pp. 734-736, Dec. 2002.
29. Y. Mitani, "Influence of nitrogen in ultra-thin SiON on negative bias temperature instability under AC stress," in IEDM Tech. Dig., 2004, pp. 117-120.
30. R. Fernández, B. Kaczer, A. Nackaerts, S. Demuynck, R. Rodríguez, M. Nafría, and G. Groeseneken, "AC NBTI studied in the 1 Hz-2 GHz range on dedicated on-chip CMOS circufts," in IEDM Tech. Dig., 2006, pp. 1-4.
31. C. Shen, M.-F. Li, C. E. Foo, T. Yang, D. M. Huang, A. Yap, G. S. Samudra, and Y.-C. Yeo, "Characterization and physical origin of fast Vth transient in NBTI of pMOSFETs with SiON dielectric," in IEDM Tech. Dig., 2006, pp. 1-4.
32. 2 gate stacks," in IEDM Tech. Dig., 2006, pp. 1-4.
33. S. Lombardo, J. H. Stathis, B. P. Linder, K. L. Pey, F. Palumbo, and C. H. Tung, "Dielectric breakdown mechanisms in gate oxides," J. Appl. Phys., vol. 98, no. 12, pp. 1-36, Dec. 2005.
34. P. E. Nicollian, W. R. Hunter, and J. C. Hu, "Experimental evidence for voltage driven breakdown models in ultrathin gate oxides," in Proc. Int. Rel. Phys. Symp., 2000, pp. 7-15.
35. E. Y. Wu, A. Vayshenker, E. Nowak, J. Suñé, R.-P. Vollertsen, W. Lai, and D. Harmon, "Experimental evidence of tbd power-law for voltage dependence of oxide breakdown in ultra thin gate oxides," IEEE Trans. Electron Devices, vol. 49, no. 12, pp. 2244-2253, Dec. 2002.
36. M.-S. Liang, S. Haddad, W. Cox, and S. Cagnina, "Degradation of very thin gate oxide MOS devices under dynamic high field/current stress," in IEDM Tech. Dig., 1986, pp. 394-398.
37. Y. Fong, I. C. Chen, S. Holland, J. Lee, and C. Hu, "Dynamic stressing of thin oxides," in IEDM Tech. Dig., 1986, pp. 664-667.
38. E. Rosenbaum, Z. Liu, and C. Hu, "Silicon dioxide breakdown lifetime enhancement under bipolar bias conditions," IEEE Trans. Electron Devices, vol. 40, no. 12, pp. 2287-2295, Dec. 1993.
39. 2 films under static and dynamic stress," IEEE Trans. Electron Devices, vol. 44, no. 5, pp. 801-808, May 1997.
40. G. Ghidini, D. Brazzelli, C. Clementi, and F. Pellizzer, "Charge trapping mechanism under dynamic stress and its effect on failure time," in Proc. Int. Rel. Phys. Symp., 1999, pp. 88-92.
41. 2 gate dielectrics under pulsed biased stress," IEEE Electron Device Lett., vol. 22, no. 5, pp. 224-226, May 2001.
42. E. Y. Wu, J. Suñé, and W. Lai, "On the Weibull shape factor of intrinsic breakdown of dielectric films and its accurate experimental determination - Part II: Experimental results and the effects of stress conditions," IEEE Trans. Electron Devices, vol. 49, no. 12, pp. 2141-2150, Dec. 2002.