Evaluating the impact of dynamic binary translation systems on hardware cache performance

2008 IEEE International Symposium on Workload Characterization, IISWC'08

Volumn , Issue , 2008, Pages 131-140

  Ruiz Alvarez, Arkaitz ^a   Hazelwood, Kim ^a  

^a UNIVERSITY OF VIRGINIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MISSES; CACHE PERFORMANCES; CACHE SIZES; CODE LAYOUTS; DATA CACHES; DYNAMIC BINARY TRANSLATIONS; EXHAUSTIVE ANALYSIS; HARDWARE PERFORMANCE COUNTERS; INSTRUMENTATION TOOLS; L2 CACHES; MICROARCHITECTURE; OVERALL PERFORMANCES; PERFORMANCE DEGRADATIONS; PROGRAM INSTRUMENTATIONS; SOFTWARE CODES; SPATIAL LOCALITIES; TRACE CACHES; TRACE LENGTHS; TWO AXES;

APPLICATIONS; BINARY CODES; BUFFER STORAGE; CACHE MEMORY; DEGRADATION; INSTRUMENTS; PROGRAM TRANSLATORS; TRANSLATION (LANGUAGES);

CODES (SYMBOLS);

EID: 56449127988     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IISWC.2008.4636098     Document Type: Conference Paper

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