Optical inspection of wafers using large-area defect detection and sampling

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 1992-November, Issue , 1992, Pages 12-21

  Riley, S L ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN FOR TESTABILITY; FAULT TOLERANCE; INSPECTION; OPTICAL TESTING; VLSI CIRCUITS;

AUTOMATIC SAMPLING; DEFECT DETECTION; ELECTRICAL TESTS; MANUFACTURING LINES; MONITOR AND CONTROL; OPTICAL INSPECTION; PHYSICAL SIGNIFICANCE; SEMICONDUCTOR MANUFACTURERS;

DEFECTS;

EID: 5644259089     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.1992.224365     Document Type: Conference Paper

References (8)

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3. C. H. Stapper, "Fact and Fiction in Yield Modeling", Microelectronics Journal 20, 129-151 (Spring 1989).
4. C. H. Stapper, "Large-Area Fault Clusters and Fault Tolerance in VLSI Circuits: A Review", IBM J. Res. Develop. 33, 162-173 (March 1989).
5. C. H. Stapper, "Small-Area Fault Clusters and Fault Tolerance in VLSI Circuits", IBM J. Res. Develop. 33, 174-177 (March 1989).
6. D. Betel, et al, "Correlating Observable Defects and Yield", Semiconductor International 14, 128-130 (October 1991).
7. C. H. Stapper, "Fault Simulation Programs for Integrated-Circuit Yield Estimations", IBM J. Res. Develop. 33, 601-674 (November 1989).
8. J. Cunningham, "The Use and Refinement of Yield Models in Integrated Circuit Manufacturing", IEEE Transactions Semiconductor Manufacturing 3, 60-71 (May 1990).