A 1 Mb/s digital subscriber line transceiver signal processor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1993, Pages 26-27

  Kuczynski, M A ^a   Lao, W ^a   Dong, A M ^a   Wong, B C ^a   Nicholas, H T ^a   Itri, B A ^a   Samueli, H ^b  

^a PairGain Technologies   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; DECISION FEEDBACK EQUALIZERS; DIGITAL SIGNAL PROCESSORS; DSL; ECHO SUPPRESSION; INTERSYMBOL INTERFERENCE; MODEMS; TELEPHONE LINES; TRANSCEIVERS;

ADC(ANALOG-TO-DIGITAL CONVERTER); ECHO CANCELLER; ERROR VALUES; EUROPEAN STANDARDS; FEEDFORWARD EQUALIZER; HIGH BIT RATES; SIGNAL PROCESSOR; SYMBOL-DECISION;

DIGITAL SUBSCRIBER LINES;

EID: 5644248863     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.1993.280099     Document Type: Conference Paper

References (2)

1. "Generic Requirements for High-bit-rate Digital Subscriber Lines", Bellcore, TA-NWT-001210, Issue 1, Oct. 1991.
2. Amrany, D., S. Gadot, M. Dimyan, "A Programmable DSP Engine for High-Rate Modems", ISSCC DIGEST OF TECHNICAL PAPERS, pp. 222-223, Feb. 1992.