A 1.2-GHz comparator with adaptable offset in 0.35-μm CMOS

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 55, Issue 9, 2008, Pages 2584-2594

  Wong, Yanyi Liu ^a,b   Cohen, Marc H ^a,c   Abshire, Pamela A ^a  

^a UNIVERSITY OF MARYLAND   (United States)

^b Virage Logic   (United States)

^c SNA International   (United States)

Author keywords

Adaptive systems; Analog memories; Analog digital conversion; Calibration; CMOS analog integrated circuits (ICs); Comparators; Floating gate; High speed ICs; Hot carriers; Offset cancellation

Indexed keywords

ADAPTIVE SYSTEMS; ANALOG INTEGRATED CIRCUITS; ANALOG TO DIGITAL CONVERSION; AUTOMATIC PROGRAMMING; CALIBRATION; CMOS INTEGRATED CIRCUITS; COMPARATORS (OPTICAL); HOT CARRIERS; NONVOLATILE STORAGE;

ANALOG MEMORY; CMOS ANALOG INTEGRATED CIRCUITS; FLOATING GATES; HIGH-SPEED ICS; OFFSET CANCELLATION;

COMPARATOR CIRCUITS;

EID: 56349095597     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2008.918010     Document Type: Article

References (40)

1. B. Razavi and B. Wooley, "Design techniques for high-speed, highresolution comparators," IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1916-1926, Dec. 1992.
2. G. Al-Rawi, "A newoffset measurement and cancellation technique for dynamic latches," in Proc. IEEE ISCAS, May 2002, vol. 1, pp. 149-152.
3. W. Yang, D. Kelly, L. Mehr,M. Sayuk, and L. Singer, "A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input," IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1931-1936, Dec. 2001.
4. J. Guilherme, P. Figueiredo, P. Azevedo, G. Minderico, A. Leal, J. Vital, and J. Franca, "A pipeline 15-b 10-Msample/s analog-to-digital converter for ADSL applications," Proc. IEEE ISCAS, vol. 1, pp. 396-399, May 2001.
5. S.-B.You, K.-W. Lee, H. C. Choi, H.-J. Park, J.-W. Kim, and P. Chung, "A 3.3 V 14-bit 10 MSPS calibration-free CMOS pipelined A/D converter," in Proc. IEEE ISCAS, May 2000, vol. 1, pp. 435-438.
6. D.-Y. Chang and U.-K. Moon, "A 1.4-V 10-bit 25-MS/s pipelined ADC using opamp-reset switching technique," IEEE J. Solid-State Circuits, vol. 38, no. 8, pp. 1401-1404, Aug. 2003.
7. H. van der Ploeg and R. Remmers, "A 3.3v 10 b 25Msample/s two-step ADC in 0.35μ CMOS," in Proc. IEEE Int. Solid-State Circuits Conf., Feg. 1999, pp. 318-319.
8. P. Figueiredo and J. Vital, "Analysis of the averaging technique in flash ADCs," in Proc. IEEE ISCAS, May 2003, vol. 1, pp. 849-852.
9. O. Carnu and A. Leuciuc, "Optimal offset averaging for flash and folding A/D converters," in Proc. IEEE ISCAS, May 2004, vol. 1, pp. 133-136.
10. M. Choi and A. Abidi, "A 6-b 1.3-Gsample/s A/D converter in 0.35-μm CMOS," IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1847-1858, Dec. 2001.
11. G. Geelen, "A 6b 1.1 Gsample/s CMOS A/D converter," in Proc. IEEE Int. Solid-State Circuits Conf., May 2001, pp. 128-129.
12. U.-K. Moon and B.-S. Song, "Background digital calibration techniques for pipelined ADCs," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 33, no. 12, pp. 102-109, Feb. 1997.
13. D. Fu, K. Dyer, S. Lewis, and P. Hurst, "A digital background calibration technique for time-interleaved analog-to-digital converters," IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1904-1911, Dec. 1998.
14. S. Jamal, D. Fu, P. Hurst, and S. Lewis, "A 10-b 120-MSample/s time-interleaved analog-to-digital converter with digital background calibration," in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2002, vol. 1, pp. 172-457.
15. X. Wang, P. Hurst, and S. Lewis, "A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration," IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1799-1808, Nov. 2004.
16. C.-C. Huang and J.-T. Wu, "A statistical background calibration technique for flash analog-to-digital converters," in Proc. IEEE ISCAS, May 2004, vol. 1, pp. 125-128.
17. Y. Wong, P. Abshire, and M. Cohen, "Floating gate comparator with automatic offset manipulation capability," in Proc. IEEE ISCAS, May 2004, vol. 1, pp. I-529-532.
18. Y. L. Wong, M. H. Cohen, and P. A. Abshire, "Differential hot electron injection in an adaptive floating gate comparator," Analog Integr. Circuits Signal Process., vol. 43, no. 3, pp. 281-296, Jun. 2005.
19. Y. L. Wong, M. H. Cohen, and P. A. Abshire, "A floating-gate comparator with automatic offset adaptation for 10-bit data conversion," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 7, pp. 1316-1326, Jul. 2005.
20. M. Cohen and G. Cauwenberghs, "Floating-gate adaptation for focal-plane online nonuniformity correction," IEEE Trans. Circuits Syst. II, vol. 48, no. 1, pp. 83-89, Jan. 2001.
21. S. Shah and S. Collins, "A temperature independent trimmable current source," in Proc. IEEE ISCAS, May 2002, vol. 1, pp. 713-716.
22. S. Jackson, J. Killens, and B. Blalock, "A programmable current mirror for analog trimming using single poly floating-gate devices in standard CMOS technology," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 48, no. 1, pp. 100-102, Jan. 2001.
23. J. Hyde, T. Humes, C. Diorio, M. Thomas, and M. Figueroa, "A 300-MS/s 14-bit digital-to-analog converter in logic CMOS," IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 734-740, May 2003.
24. P. Hasler, B. Minch, and C. Diorio, "An autozeroing floating-gate amplifier," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 48, no. 1, pp. 74-82, Jan. 2001.
25. T. Constandinou, J. Georgiou, and C. Toumazou, "An auto-input-offset removing floating gate pseudo-differential transconductor," in Proc. IEEE ISCAS, May 2003, vol. 1, pp. 169-172.
26. Y.Wong, M. Cohen, and P. Abshire, "A 1.2 GHz adaptive floating gate comparator with 13-bit resolution," in Proc. IEEE ISCAS, May 2005, pp. 6146-6149.
27. P. Hasler and J. Dugger, "Correlation learning rule in floating-gate pFET synapses," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 48, no. 1, pp. 65-73, Jan. 2001.
28. K. Rahimi, C. Diorio, C. Hernandez, and M. Brockhausen, "A simulation model for floating-gate MOS synapse transistors," in Proc. IEEE ISCAS, May 2002, vol. 2, pp. 532-535.
29. M. Cohen and G. Cauwenberghs, "CMOS imager non-uniformity correction using floating-gate adaptation," in CMOS Imagers: From Phototransduction to Image Processing, O. Y. Pecht and R. E. Cummings, Eds. Norwell, MA: Kluwer, 2004, ch. 6.
30. P. Hasler, B. A. Minch, and C. Diorio, "Adaptive circuits using pFET floating-gate devices," in Proc. Advanced Res. VLSI, 1999, pp. 215-229.
31. D. W. Graham, E. Farquhar, B. Degnan, C. Gordon, and P. Hasler, "Indirect programming of floating-gate transistors," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 5, pp. 951-963, May 2007.
32. C. A. Mead, "Adaptive retina," in Analog VLSI Implementations of Neural Systems. Norwell, MA: Kluwer, 1989.
33. E. Rosenbaum, R. Rofan, and C. Hu, "Effect of hot-carrier injection on n- and pMOSFET gate oxide integrity," IEEE Electron Device Lett., vol. 12, no. 11, pp. 599-601, Nov. 1991.
34. B. Kaczar, R. Degraeve, G. Groeseneken, M. Rasras, S. Kubicek, E. Vandamme, and G. Badenes, "Effect of hot-carrier injection on nand pMOSFET gate oxide integrity," in IEDM Tech. Dig., 2000, pp. 553-556.
35. MOSIS Scalable CMOS (SCMOS) Design Rules rev. 8.00 Oct. 2004 Online. Available: http://www.mosis.org/Technical/Designrules/scmos/ scmos-main.html, MOSIS
36. J. Yuan and C. Svensson, "New single-clock CMOS latches and flipflops with improved speed and power savings," IEEE J. Solid-State Circuits vol. 32, no. 1, pp. 62-69, Jan. 1997.
37. L. Dai and R. Harjani, Design of High Performance CMOS Voltage-Controlled Oscillators. Boston, MA: Kluwer, 2003.
38. H. W. Johnson and M. Graham, High-Speed Digital Design: A Handbook of Black Magic. Englewood Cliffs, NJ: Prentice-Hall, 1993.
39. P. Xu, Y. Wong, T. Horiuchi, and P. Abshire, "Compact floating-gate true random number generator," Electron. Lett., vol. 42, no. 23, pp. 1346-1347, Nov. 2006.
40. Y. Wong, M. Cohen, and P. Abshire, "On-line histogram equalization for flash ADC," in Proc. IEEE ISCAS, May 2007, pp. 3598-3601.