A fault tolerance scheme for hierarchical dynamic schedulers in grids

Proceedings of the International Conference on Parallel Processing Workshops

Volumn , Issue , 2008, Pages 53-58

  Gorde, Nitin B ^a   Aggarwal, Sanjeev K ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY KANPUR   (India)

Author keywords

[No Author keywords available]

Indexed keywords

ERRORS; FAULT TOLERANCE; HYDRODESULFURIZATION; MICROPROCESSOR CHIPS; RELIABILITY; SCHEDULING; TECHNICAL PRESENTATIONS;

DYNAMIC GRIDS; DYNAMIC SCHEDULERS; GRID WORKFLOW; HIERARCHY TREES; RECOVERY PROCESSES; RESOURCE FAILURES; SCHEDULING PROCESSES; SIMULATION RESULTS; SINGLE POINTS;

QUALITY ASSURANCE;

EID: 55749100502     PISSN: 15302016     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP-W.2008.7     Document Type: Conference Paper

References (10)

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