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Volumn 1, Issue 1, 1989, Pages 9-24
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Bit-Level systolic architectures for high performance IIR filtering
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Author keywords
[No Author keywords available]
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Indexed keywords
COMPUTER ARCHITECTURE;
COMPUTER HARDWARE;
COMPUTER SYSTEMS, DIGITAL--PIPELINE PROCESSING;
INTEGRATED CIRCUITS, VLSI;
BIT-LEVEL SYSTOLIC ARCHITECTURES;
FEEDBACK LOOP LATENCY;
HIGH PERFORMANCE IIR FILTERING;
REDUNDANT ARITHMETIC;
WORDLENGTH INDEPENDENT LATENCY;
ELECTRIC FILTERS, DIGITAL;
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EID: 5544302589
PISSN: 09225773
EISSN: 1573109X
Source Type: Journal
DOI: 10.1007/BF00932062 Document Type: Article |
Times cited : (25)
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References (18)
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