Deep-submicron CMOS technologies for low-power and high-performance operation

Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)

Volumn 79, Issue 11, 1996, Pages 1-9

  Deura, Manabu ^a   Nara, Yasuo ^a   Yamazaki, Tatsuya ^a   Gotoh, Kenichi ^a   Ohtake, Fumio ^a   Kurata, Hajime ^a   Sugii, Toshihiro ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

Counter dose; Deep submicron; Double side walls; Extension; Low Vth

Indexed keywords

ELECTRIC RESISTANCE; HOT CARRIERS; INTEGRATED CIRCUIT LAYOUT;

COBALT SILICIDE PROCESS; COUNTER DOSE PROCESS; DEEP SUBMICRON CMOS; DOUBLE SIDE WALL PROCESS; LOW THRESHOLD VALUE; SHALLOW EXTENSION STRUCTURES; SHORT CHANNEL EFFECT;

CMOS INTEGRATED CIRCUITS;

EID: 5544284777     PISSN: 8756663X     EISSN: None     Source Type: Journal    
DOI: 10.1002/ecjb.4420791101     Document Type: Article

References (6)

1. T. Yamazaki, K. Goto, T. Fukano, Y. Nara, T. Sugii, and T. Ito. 21psec switching 0.1 μm-CMOS at room temperature using high performance Co silicide process. IEDM Tech. Dig., Washington, D.C., pp. 906-909 (Dec. 1993).
2. Y. Nara, M. Deura, K. Goto, T. Yamazaki, T. Fukano, and T. Sugii. Fabrication and delay time analysis of deep submicron CMOS. IEICE Trans. Electron., E78-C, 3 (March 1995).
3. K. Goto, T. Yamazaki, A. Fushida, S. Inagaki, and H. Yagi. Optimization of silicide process for 0.1 μm-CMOS device. Symp. on VLSI Tech., Hawaii, America, pp. 119-120 (June 1994).
4. nd DRC. Dig., Colorado, IVA-1 (June 1994).
5. Y. Takao, K. Watanabe, and S. Kawamura. Impact of Source-Drain extension dose on hot carrier reliability in 0.1 μm NMOSFET. Extended Abstract of SSDM Dig., Yokohama, pp. 506-508 (Aug. 1994).
6. H. Ishida, A. Shimizu, N. Ohki, T. Yamanaka, and T. Nagano. 0.25 μm buried channel PMOSFET using a thin film amorphous Si through channel doping, IEICE Tech. Rept., SDM94-43 (July 1994).