Optimization of fluorine co-implantation for PMOS source and drain extension formation for 65nm technology node

Materials Research Society Symposium - Proceedings

Volumn 810, Issue , 2004, Pages 247-252

  Graoui, H ^a   Hilkene, M ^a   McComb, B ^a   Castle, M ^a   Felch, S ^a   Cowern, N E B ^b   Al Bayati, A ^a   Tjandra, A ^a   Foad, M A ^a  

^a APPLIED MATERIALS INC   (United States)

^b UNIVERSITY OF SURREY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

AMORPHIZATION; ANNEALING; ELECTRIC RESISTANCE; FLUORINE; ION IMPLANTATION; PROBABILITY;

ENERGY RATIO; FLUORINE ENERGY; SHEET RESISTANCE; TRANSIENT ENHANCED DEFECTS (TED);

CMOS INTEGRATED CIRCUITS;

EID: 5544224561     PISSN: 02729172     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1557/proc-810-c5.8     Document Type: Conference Paper

References (5)

1. L. S. Robertson et al. IEEE 2000, pp 171-174.
2. C. Dachs et al, Ultra Shallow Junctions 2003 proceedings, pp 15.
3. L.S Robertson IEEE 2000. pp 171.
4. B. Colombeau et al., in these proceedings.
5. Y.Matsunaga and M.A. Foad, Patent number: US 6583018 B1, June 2003