Neuronal processing, reconfigurable neural networks and stochastic computing

2008 8th IEEE Conference on Nanotechnology, IEEE-NANO

Volumn , Issue , 2008, Pages 717-720

  Lyshevski, Sergey ^a   Shmerko, Vlad ^b   Lyshevski, Marina ^c   Yanushkevich, Svetlana ^b  

^a Rochester Institute of Technology   (United States)

^b UNIVERSITY OF CALGARY   (Canada)

^c Microsystems and Nanotechnologies   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; NANOTECHNOLOGY; THREE DIMENSIONAL; VECTORS;

COMPUTING HARDWARES; DESIGN ALGORITHMS; DESIGN METHODS; DIMENSIONAL SPACES; LIVING SYSTEMS; MOLECULAR ENGINEERINGS; MOLECULAR PROCESSING; NATURAL COMPUTING; NATURAL PROCESSING; NEUROCOMPUTING; NEURONAL PROCESSING; PROCESSING PLATFORMS; RECONFIGURABLE; VECTOR PROCESSING;

NEURAL NETWORKS;

EID: 55349129236     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NANO.2008.216     Document Type: Conference Paper

References (6)

1. S. E. Lyshevski, Molecular Electronics, Circuits, and Processing Platforms, CRC Press, Boca Raton, FL, 2007.
2. S. N. Yanushkevich, S. E. Lyshevski and V. P. Shmerko, Computer Arithmetics for Nanoelectronics, CRC Press, Boca Raton, FL, 2008.
3. S. N. Yanushkevich, V. P. Shmerko and S. E. Lyshevski, Logic Design of NanoICs, CRC Press, Boca Raton, FL, 2005.
4. A. Al-Rabady and M. Perkowski, "Shannon and Davio sets of new lattice structures for logic synthesis in three-dimensional space," Proc. 5th Int. Workshop on Applications of the Reed-Muller Expansion in Circuit Design, Mississippi State University, pp.165-184, 2001.
5. S. Y. Kung, VLSI Array Processors, Prentice Hall, Upper Saddle River, NJ, 1988.
6. S. Haykin, Neural Networks: A Comprehensive Foundation. Prentice Hall, Upper Saddle River, NJ, 1999.