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Volumn 47, Issue 6 PART 2, 2008, Pages 4893-4897
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Hot-spot detection and correction using full-chip-based process window analysis
a
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Author keywords
Design; DfM; Hot spot; Lithography; OPC; Process window
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Indexed keywords
COMPUTER AIDED DESIGN;
DESIGN;
ELECTRIC CONDUCTIVITY;
ERROR CORRECTION;
MACHINE DESIGN;
MASKS;
SCANNING;
SEMICONDUCTING INDIUM;
SEMICONDUCTOR DEVICE MANUFACTURE;
SEMICONDUCTOR DEVICE MODELS;
SEMICONDUCTOR DEVICES;
SEMICONDUCTOR MATERIALS;
SEMICONDUCTOR SWITCHES;
SENSITIVITY ANALYSIS;
SHRINKAGE;
TECHNOLOGICAL FORECASTING;
WINDOWS;
CHIP SIZES;
COMPACT DESIGNS;
DESIGN FOR MANUFACTURABILITY;
DESIGN LAYOUTS;
DFM;
ELECTRONIC DESIGN AUTOMATION COMPANIES;
HIGH YIELDS;
HIGH-DENSITY;
HOT SPOT;
IMAGE LOGS;
IMMERSION SCANNERS;
INDEX PARAMETERS;
KEY SOLUTIONS;
LITHOGRAPHY SIMULATIONS;
MASK ERROR ENHANCEMENT FACTORS;
NUMERICAL APERTURES;
OPC;
OPTICAL PROXIMITY CORRECTIONS;
PATTERN SIZES;
PROCESS MARGINS;
PROCESS WINDOW;
PROCESS WINDOW ANALYSES;
PROCESS WINDOWS;
QUALITY DESIGNS;
QUANTITATIVE;
SEMICONDUCTOR INDUSTRIES;
SPOT DETECTIONS;
TECHNOLOGY DEVELOPMENTS;
PROCESS ENGINEERING;
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EID: 55049135314
PISSN: 00214922
EISSN: 13474065
Source Type: Journal
DOI: 10.1143/JJAP.47.4893 Document Type: Article |
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Times cited : (2)
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References (3)
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