Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization

Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2008, Pages 699-700

  Paulsson, Katarina ^a   Hübner, Michael ^a   Becker, Jürgen ^a  

^a UNIVERSITY OF KARLSRUHE   (Germany)

Author keywords

Reconfiguration, Power optimization

Indexed keywords

COMPUTER HARDWARE; RECONFIGURABLE ARCHITECTURES;

DYNAMIC AND PARTIAL RECONFIGURATION; ON DEMANDS; RECONFIGURATION , POWER OPTIMIZATION; RUNTIME ADAPTATION; RUNTIMES; SELF-OPTIMIZATION;

RECONFIGURABLE HARDWARE;

EID: 54949150313     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2008.4630044     Document Type: Conference Paper

References (5)

1. K. Paulsson, M. Hübner, J. Becker: "On-Line Optimization of FPGA Power-Dissipation by Exploiting Run-time Adaptation of Communication Primitives", SBCCI2006, Brazil
2. K. Paulsson, M. Hübner, J. Becker, J.-M. Philippe, C. Gamrat: "On-line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations Within the Æther Project", FPL 2007, Amsterdam, Netherlands
3. K. Paulsson, M. Hübner, S. Bayar, J. Becker: "Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems", ReCoSoc2007, Montpellier, France
4. K. Paulsson, G. Auer, M. Dreschmann, M. Hübner, J. Becker: "Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self- Reconfiguration on Xilinx Spartan III FPGAs", FPL 2007, Amsterdam, Netherlands
5. N. J. Steiner, "A Standalone Wire Database for Routing and Tracing in Xilinx Virtex, Virtex-E, and Virtex-II FPGAs, "Master's thesis, Virginia Polytechnic Institute and State University, 2002.