ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS process

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2002-January, Issue , 2002, Pages 331-336

  Ker, Ming Dou ^a   Chuang, Chien Hui ^a   Hsu, Kuo Chun ^a   Lo, Wen Yu ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b Silicon Integrated Systems group   (Taiwan)

Author keywords

Circuits; CMOS process; CMOS technology; Electrostatic discharge; MOS devices; MOSFETs; Power supplies; Protection; Robustness; Voltage

Indexed keywords

CMOS INTEGRATED CIRCUITS; DESIGN; ELECTRIC POTENTIAL; ELECTROSTATIC DISCHARGE; INTEGRATED CIRCUIT DESIGN; MOS DEVICES; MOSFET DEVICES; NETWORKS (CIRCUITS); ROBUSTNESS (CONTROL SYSTEMS); SUBSTRATES; VOLTAGE CONTROL;

CMOS PROCESSS; CMOS TECHNOLOGY; MOSFETS; POWER SUPPLY; PROTECTION;

ELECTROSTATIC DEVICES;

EID: 5444224707     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2002.996768     Document Type: Conference Paper

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