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Volumn 36, Issue 1, 2009, Pages 634-642

A new variable topology for evolutionary hardware design

Author keywords

Evolutionary hardware design; Genetic algorithm; Routing graph; Slicing structure

Indexed keywords

CURVE FITTING; ELECTRIC CURRENTS; LOGIC CIRCUITS; SWITCHING CIRCUITS; SWITCHING THEORY; TOPOLOGY;

EID: 53849143966     PISSN: 09574174     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.eswa.2007.09.017     Document Type: Article
Times cited : (7)

References (15)
  • 6
    • 0000718899 scopus 로고
    • A map method for synthesis of combinational logic circuit, transaction of the American Institute of Electrical Engineers
    • Karnaugh M. A map method for synthesis of combinational logic circuit, transaction of the American Institute of Electrical Engineers. Communications and Electronics 72 (1953) 593-599
    • (1953) Communications and Electronics , vol.72 , pp. 593-599
    • Karnaugh, M.1
  • 10
    • 33845331515 scopus 로고
    • Minimization of Boolean function
    • McCluskey E.J. Minimization of Boolean function. Bell System Technical Journal 35 5 (1956) 1417-1444
    • (1956) Bell System Technical Journal , vol.35 , Issue.5 , pp. 1417-1444
    • McCluskey, E.J.1
  • 12
    • 0000316190 scopus 로고
    • A way to simplify truth function
    • Quine W.V. A way to simplify truth function. American Mathematical Monthly 62 9 (1955) 627-631
    • (1955) American Mathematical Monthly , vol.62 , Issue.9 , pp. 627-631
    • Quine, W.V.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.