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Volumn 2, Issue , 2006, Pages 1571-1576
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Use of accurate chip level modeling and analysis of a power module to establish reliability rules
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Author keywords
[No Author keywords available]
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Indexed keywords
ACTIVE FILTERS;
ELECTRIC CONDUCTIVITY;
INDUSTRIAL ELECTRONICS;
INSULATED GATE BIPOLAR TRANSISTORS (IGBT);
RELIABILITY;
RELIABILITY ANALYSIS;
SEMICONDUCTING INDIUM;
SEMICONDUCTOR MATERIALS;
CHIP-LEVEL;
COUPLING PHENOMENON;
ELECTRICAL BEHAVIORS;
INTERNATIONAL SYMPOSIUM;
MODELING AND ANALYSIS;
MODELING APPROACHES;
POWER MODULES;
SIMULATION APPROACH;
SIMULATION METHODOLOGY;
ELECTRIC NETWORK ANALYSIS;
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EID: 53649087979
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/ISIE.2006.295706 Document Type: Conference Paper |
Times cited : (6)
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References (6)
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