Concepts of switching in the time-triggered network-on-chip

Proceedings - 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2008

Volumn , Issue , 2008, Pages 120-129

  Paukovits, Christian ^a   Kopetz, Hermann ^a  

^a VIENNA UNIVERSITY OF TECHNOLOGY   (Austria)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION SUB SYSTEMS; INTERNATIONAL CONFERENCES; NETWORK ON CHIPS; NETWORK-ON-CHIP; PROTOTYPE IMPLEMENTATIONS; REAL-TIME COMPUTING SYSTEMS; SWITCHING ALGORITHMS; SWITCHING COMPONENTS; SYSTEM ON CHIPS; TIME-TRIGGERED;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER SYSTEMS; ELECTRIC NETWORK TOPOLOGY; EMBEDDED SYSTEMS; INTEGRATED CIRCUITS; NETWORK PROTOCOLS; SENSOR NETWORKS; SWITCHING;

REAL TIME SYSTEMS;

EID: 53549131547     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTCSA.2008.18     Document Type: Conference Paper

References (18)

1. D. Bertozzi and L. Benini, Xpipes: a network-on-chip architecture for gigascale systems-on-chip. Circuits and Systems Magazine, IEEE, 4(2): 18-31, April - June 2004.
2. W. Dally and B. Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 2003.
3. P. Gelsinger. Microprocessors for the new millenium, challenges, opportunities, and new frontiers. In Proc. of the Solid State Circuit Conference. IEEE Press, 2001.
4. K. Goossens, J. Dielissen, and A. Radulescu. The Æthereal network on chip: Concepts, architectures, and implementations. IEEE Design and Test of Computers, 22(5): 414-421, 2005.
5. B. Huber. Resource Management in an Integrated Time-Triggered Architecture. PhD thesis, Technische Universität Wien, Institut für Technische Informatik, Treitlstr. 3/3/182-1, 1040 Vienna, Austria, 2008.
6. H. Kopetz. Pulsed data streams. In IFIP TC 10 Working Conference on Distributed and Parallel Embedded Systems (DIPES 2006), pages 105-124, Braga, Portugal, Oct. 2006. Springer.
7. H. Kopetz and G. Bauer. The time-triggered architecture. Proceedings of the IEEE, 91(1): 112-126, Jan. 2003.
8. H. Kopetz and R. Obermaisser. Temporal composability. Computing & Control Engineering Journal, 13: 156-162, Aug. 2002.
9. R. Obermaisser, H. Kopetz, C. E. Salloum, and B. Huber. Error containment in the time-triggered system-on-a-chip architecture. International Embedded Systems Symposium (IESS'07), Jun. 2007.
10. R. Obermaisser, P. Peti, B. Huber, and C. E. Salloum. De-cos: An integrated time-triggered architecture, e & i journal (journal of the Austrian professional institution for electrical and information engineering), 3, Mar. 2006.
11. H. Paulitsch, R. Obermaisser, C. E. Salloum, B. Huber, and H. Kopetz. A diagnostic unit for the time-triggered system-on-a-chip architecture. DATE07 Workshop on Diagnostic Services in Network-on-Chips - Test, Debug, and On-Line Monitoring, Apr. 2007.
12. S. Poledna. Replica determinism in distributed real-time systems: A brief survey. Research Report 6/1993, Technische Universität Wien, Institut für Technische Informatik, Treitlstr. 1-3/182-1, 1040 Vienna, Austria, 1993.
13. A. Radulescu, J. Dielissen, K. Goossens, E. Rijpkema, and P. Wielage. An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration.
14. C. E. Salloum. Interface Design in the Time-Triggered System-on-Chip Architecture. PhD thesis, Technische Universität Wien, Institut für Technische Informatik, Treitlstr. 3/3/182-1, 1040 Vienna, Austria, 2008.
15. C. E. Salloum, R. Obermaisser, B. Huber, H. Paulitsch, and H. Kopetz. A time-triggered system-on-a-chip architecture with integrated support for diagnosis. DATE07 Workshop on Diagnostic Services in Network-on-Chips - Test, Debug, and On-Line Monitoring, Apr. 2007.
16. S. I. A. (SIA). International technology roadmap for semiconductors. Technical report, Semiconductor Industry Association (SIA), 2005.
17. J. Sifakis. A framework for component-based construction. In Proc. of 3rd IEEE Int. Conference on Software Engineering and Formal Methods (SEFM05), pages 293-300, Sept. 2005.
18. W. Wolf. The future of multiprocessors systems on chips. In Proc. of the Design Automation conference. IEEE Press, 2004.