Low power technology mapping for LUT based FPGA - A genetic algorithm approach

Proceedings of the IEEE International Conference on VLSI Design

Volumn 2003-January, Issue , 2003, Pages 79-84

  Pandey, R ^a   Chattopadhyay, S ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY GUWAHATI   (India)

Author keywords

Biological cells; Capacitance; Combinational circuits; Field programmable gate arrays; Genetic algorithms; Logic circuits; Minimization; Switches; Switching circuits; Table lookup

Indexed keywords

ALGORITHMS; BIOINFORMATICS; CAPACITANCE; CHOPPERS (CIRCUITS); COMBINATORIAL CIRCUITS; DESIGN; EMBEDDED SOFTWARE; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); GENETIC ALGORITHMS; INTEGRATED CIRCUITS; MAPPING; OPTIMIZATION; SWITCHES; SWITCHING CIRCUITS; SYSTEMS ANALYSIS; TABLE LOOKUP; VLSI CIRCUITS;

BIOLOGICAL CELLS; EFFICIENT GENETIC ALGORITHMS; FPGA TECHNOLOGY; GENETIC ALGORITHM APPROACH; LOW POWER TECHNOLOGIES; POWER MINIMIZATION; TRANSITION ACTIVITY; TRANSITION PROBABILITIES;

LOGIC CIRCUITS;

EID: 52949126571     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICVD.2003.1183118     Document Type: Conference Paper

References (15)

1. Jan-Min Hwang, Feng-Yi Chiang, and TingTing Hwang. A Re-engineering Approach to Low Power FPGA Design Using SPDF. DAC-1998.
2. Balakrishna Kumthekar, Luca Benini, Enrico Macii, and Fabio Somenzi. In-Place Power Optimization for LUT-Based FPGAs. DAC-98.
3. Chau-Chin Wang, and Cheng-Pin Kwan. An Analysis of Low Power Technology Mapping by Hiding High-Transition Paths in Invisible Edges for LUT-Based FPGAs. 1997 IEEE International Symposium on Circuits and System. pp. 1536-1539. 1997.
4. V. Tiwari, P. Ashar, and S. Malik. Technology mapping for low power. 30th ACM/IEEE Design Automation Conference. pp. 74-79. 1993.
5. C-Y. Tsui, M. Pedram, and A. D. Despain. Technology decomposition and mapping targeting low power dissipation. 30th ACM/IEEE Design Automation Conference. pp. 68-73. 1993.
6. R. Murgai, R. Brayton, and A Sangiovanni-Vincentelli. Logic Synthesis For Field Programmable Gate Arrays. Kluwer academic publication. 1995.
7. E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, and R. K. Brayton. SIS: A system for sequential circuit synthesis. Technical report UCB/ERL M92/41, University of California, Berkeley, May 1992.
8. F. N. Najm. A Survey of Power Estimation Techniques in VLSI circuits. IEEE Trans. VLSI System. Vol. 2, no. 4, pp. 446-455, January 1995.
9. D. E. Goldberg. Genetic algorithm in search, optimization, and machine learning. Addison-Wesley Publishing Company. 1989.
10. Nan Zhuang and Peter Y. K. Cheung. Using Genetic Algorithm in Binate Covering for LUT-based FPGA Technology Mapping. URL: citeseer.nj.nec.com/50251.html.
11. R. Murgai, N.Shenoy, R.K. Brayton, and Sangiovanni-Vincentelli. Improved Logic Synthesis Algorithm for Table Look Up Architectures. Proc. IEEE International Conference on Computer Aided Design, 1991. pp 564-567.
12. R.J. Francis, J. Rose, K. Chung. Chortle: A Technology Mapping Program for Lookup Table based Field Programmable Gate Arrays. DAC-1990. pp. 613-619.
13. R.J. Francis, J. Rose, and Z. Vranesic. Chortle-crf: Fast Technology Mapping for Lookup Table based FPGAs. DAC-1991. pp. 227-233.
14. T.T. Hwang, R.M. Owens, M.J. Irwin, and K.H. Wang. Logic Synthesis for Field Programmable Gate Arrays. IEEE Trans. on CAD, 1994, 13(10). pp. 1280-1286.
15. J. Cong and Y. Ding. FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup Table based FPGA Design. IEEE Trans. on CAD, 1994 13(1), pp. 1-12.