Unified Convolutional/Turbo decoder design using tile-based timing analysis of VA/MAP kernel

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 16, Issue 10, 2008, Pages 1358-1371

  Li, Fan Min ^a   Lin, Cheng Hung ^a,b   Wu, An Yeu ^a,b  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b IEEE

Author keywords

Convolutional code; Forward error correction code; Log MAP; Maximum a posteriori probability; Reconfigurable FEC architecture; Turbo code; Viterbi algorithm

Indexed keywords

CODES (STANDARDS); CODES (SYMBOLS); COMMUNICATION SYSTEMS; CONFORMAL MAPPING; CONVOLUTION; CONVOLUTIONAL CODES; DATA STORAGE EQUIPMENT; ERROR CORRECTION; FORWARD ERROR CORRECTION; GRAPHIC METHODS; MAPS; STANDARDS; TIME MEASUREMENT; TURBO CODES; VIDEO STREAMING; VITERBI ALGORITHM;

3GPP STANDARDS; APPLICATION SCENARIOS; CHART ANALYSES; CMOS PROCESSING; CONVOLUTIONAL CODE; DIFFERENT SIZES; FEC DECODERS; FLEXIBLE TOOLS; FORWARD-ERROR-CORRECTION CODE; HARDWARE UTILIZATION; IDLE TIME; LOG-MAP; MAP ALGORITHMS; MAP DECODING; MAXIMUM A-POSTERIORI PROBABILITY; MEMORY SIZE; PROCESSING-ELEMENT; PROTOTYPE DESIGNS; PROTOTYPING; RECONFIGURABLE FEC ARCHITECTURE; THROUGHPUT RATES; TIMING ANALYSIS; TURBO CODE; TURBO DECODERS; VITERBI;

DECODING;

EID: 52649133391     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2000514     Document Type: Conference Paper

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