Verification of complex analog and RF IC designs

Proceedings of the IEEE

Volumn 95, Issue 3, 2007, Pages 622-639

  Chang, Henry ^a   Kundert, Ken ^a  

^a Designers Guide Consulting Inc   (United States)

Author keywords

Analog integrated circuits; Circuit modeling; Circuit simulation; Design automation; Design methodology; Hardware design languages; Integrated circuit measurements; Integrated circuit modeling; Mixed analog ndash; digital integrated circuits; Self testing

Indexed keywords

CIRCUIT SIMULATION; COMPUTER AIDED DESIGN; COMPUTER SIMULATION LANGUAGES; DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT TESTING; MODELING LANGUAGES; TIMING CIRCUITS;

CIRCUIT MODELING; DESIGN AUTOMATIONS; DESIGN METHODOLOGY; HARDWARE DESIGN LANGUAGE; INTEGRATED CIRCUIT MEASUREMENTS; INTEGRATED CIRCUIT MODELING; SELF-TESTING;

ANALOG INTEGRATED CIRCUITS;

EID: 52649112965     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2006.889384     Document Type: Article

References (37)

1. V. Aparin, G. Ballantyne, C. Persico, and A. Cicalini, "An integrated LMS adaptive filter of TX leakage for CDMA receiver front ends," in Proc. RFIC, 2005, pp. 229-232.
2. R. Bagheri, A. Mirzaei, S. Chehrazi, M. Heidari, M. Lee, M. Mokhemar, W. Tang, and A. Abidi, "An 800 MHz to 5 GHz software-defined radio receiver in 90 nm CMOS," in Proc. Int. Solid-State Circuits Conf. (ISSCC), 2006, pp. 1932-1941.
3. J. Lim, Y. Cho, K. Jung, J. Park, J. Choi, and J. Kim, "A wideband active-RC filter with a fast tuning scheme for wireless communication receivers," in Proc. IEEE Custom Integrated Circuits Conf., 2005, pp. 637-640.
4. A. Mirzaei, R. Bagheri, S. Chehrazi, and A. Abidi, "A second-order anti-aliasing prefilter for an SDR receiver," in Proc. IEEE Custom Integrated Circuits Conf., 2005, pp. 629-632.
5. K. Muhammad et al., "A discrete time quad-band GSM/GPRS receiver in a 90 nm digital CMOS process," in Proc. IEEE Custom Integrated Circuits Conf., 2005, pp. 809-812.
6. Y. Palaskas et al., "A 5 GHz class-AB power amplifier in 90 nm CMOS with digitally-assisted AM-PM correction," in Proc. IEEE Custom Integrated Circuits Conf., 2005, pp. 813-816.
7. K. S. Kundert and O. Zinke, The Designer's Guide to Verilog-AMS. Boston, MA: Kluwer, 2004.
8. K. Kundert, Principles of Top-Down Mixed-Signal Design. [Online]. Available: http://www.designers-guide.org/Design.
9. H. Chang, L. Cooke, M. Hunt, G. Martin, A. McNelly, and L. Todd, Surviving the SoC Revolution. Boston, MA: Kluwer, 1999.
10. Analog/Mixed-Signal VSI Extension Specification Version 1 2.2 (AMS 1.2.2), VSIA Analog/Mixed-Signal Development Working Group, Feb. 2001. [Online]. Available: http://www.vsi.org/.
11. B. Bailey, G. Martin, and T. Anderson, Taxonomies for the Development and Verification of Digital Systems. New York: Springer, 2005.
12. A. S. Meyer, Principles of Functional Verification. New York: Elsevier, 2003.
13. J. Holmes, F. James, and I. Getreu. (1997, Jun.). "Mixed-signal modeling for ICs," Integr. Syst. Design Mag. [Online]. Available: http://www.eetimes.com/editorial/june97.html.
14. R. B. Staszewski, C. Fernando, and P. T. Balsara, "Event-driven simulation and modeling of phase noise an RF oscillator," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 4, pp. 723-733, Apr. 2005.
15. K. Muhammad, T. Murphy, and R. B. Staszewski, "Verification of RF SoCs: RF, analog, "aseband and software," in Proc. IEEE Radio Frequency Integrated Circuits (RFIC) Symp., 2006, pp. 361-364.
16. T. Murayama and Y. Gendai, "A top-down mixed-signal design methodology using a mixed-signal simulator and analog HDL, " in Proc. EURO-DAC'96, Eur. Design Automation Conf. and Exhibition, 1996, pp. 59-64.
17. Verilog-AMS Language Reference Manual: Analog & Mixed-Signal Extensions to Verilog HDL, ver. 2.0, Open Verilog International. [Online]. Available: http://www.eda.org/verilog-ams.
18. Standard Description Language Based on the Verilog Hardware Description Language, IEEE Standard 1364-1995.
19. E. Christen and K. Bakalar, "VHDL-AMSVA hardware description language for analog and mixed-signal applications," IEEE Trans. Circuits Syst. II Analog Digit. Signal Process., vol. 46, no. 10, pp. 1263-1272, Oct. 1999.
20. P. J. Ashenden, G. D. Peterson, and D. A. Teegarden, The System Designer's Guide to VHDL-AMS. San Francisco, CA: Morgan Kaufmann, 2002.
21. VHDL Language Reference Manual, IEEE Standard 1076-1993.
22. IEEE Standard for System Verilog: Unified Hardware Design, Specification and Verification Language, IEEE Standard 1800-2005.
23. SystemC 2.1 Language Reference Manual, Open SystemC Initiative, May 2005. [Online]. Available: http://www.systemc.org.
24. Mathworks, Matlab and Simulink. [Online]. Available: http://www.mathworks.com.
25. N. Chandra and G. W. Roberts, "Top-down analog design methodology using Matlab and Simulink, " in Proc. 2001 IEEE Int. Symp. Circuits and Systems (ISCAS'01), 2001, pp. 319-322.
26. E. Lee, Overview of the Ptolemy Project, Univ. California, "erkeley, Tech. Memo. UCB/ERL M03/25, Jul. 2, 2003.
27. G. G. E. Gielen, "Modeling and analysis techniques for system-level architectural design of telecom front-ends," IEEE Trans. Microw. Theory Tech., vol. 50, pt. 2, no. 1, pp. 360-368, Jan. 2002.
28. G. G. E. Gielen, "System-level design tools for RF communication ICs, " in Proc. URSI Int. Symp. Signals, Systems, and Electronics (ISSSE'98), 1998, pp. 422-426.
29. C. Force. (1999, Feb.). Integrating design and test using new tools and techniques, EETimes. [Online]. Available: http://eetimes. com/editorial/1999/test9902.html.
30. C. Force and T. Austin, "Testing the design: The evolution of test simulation, " presented at the Int. Test Conf., Washington, DC, 1998.
31. Teradyne, SpectreVX and SaberVX Virtual Test Environments. [Online]. Available: http://www.teradyne.com.
32. H. Chang, E. Charbon, U. Choudhury, A. Demir, E. Felt, E. Liu, E. Malavasi, A. Sangiovanni-Vincentelli, and I. Vassiliou, A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits. Boston, MA: Kluwer, 1997.
33. K. Kundert, H. Chang, D. Jefferies, G. Lamant, E. Malavasi, and F. Sendig, "Design of mixed-signal systems-on-a-chip," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 19, no. 12, pp. 1561-1571, Dec. 2000.
34. E. Chou and B. Sheu, "Nanometer mixed-signal system-on-a-chip design," IEEE Circuits Devices Mag., vol. 18, no. 4, pp. 7-17, Jul. 2002.
35. J. E. Franca, "Integrated circuit teaching through top-down design," IEEE Trans. Educ., vol. 37, no. 4, pp. 351-357, Nov. 1994.
36. Cadence Design Systems, AMS Designer. [Online]. Available: http://www.cadence.com.
37. Mentor Graphics, ADVance MS Simulator. [Online]. Available: http://www.mentor.com.