A proactive wearout recovery approach for exploiting microarchitectural redundancy to extend cache SRAM lifetime

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2008, Pages 353-362

  Shin, Jeonghee ^a   Zyuban, Victor ^b   Bose, Pradip ^b   Pinkston, Timothy M ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AREA OVERHEAD; INTERNATIONAL SYMPOSIUM; LIFETIME RELIABILITY; MEAN-TIME-TO-FAILURE; MICRO ARCHITECTURES; ON-CHIP CACHES;

COMPUTER ARCHITECTURE; COMPUTER SCIENCE; COMPUTER SYSTEMS; COMPUTERS; REDUNDANCY; RELIABILITY; STATIC RANDOM ACCESS STORAGE;

QUALITY ASSURANCE;

EID: 52649086945     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2008.30     Document Type: Conference Paper

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