High level DSP synthesis using the MARS design system

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 1992, Pages 164-167

  Wang, Ching Yi ^a   Parhi, Keshab K ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA FLOW ANALYSIS; DATA FLOW GRAPHS; DATA TRANSFER; GRAPHIC METHODS; HIGH LEVEL SYNTHESIS; ITERATIVE METHODS;

ARCHITECTURE SYNTHESIS; DIGITAL SIGNAL PROCESSING (DSP); EFFICIENT ARCHITECTURE; IMPLICIT RETIMING; ITERATION BOUND; NOVEL ALGORITHM; PRECEDENCE CONSTRAINTS; RESOURCE ALLOCATION ALGORITHMS;

DIGITAL SIGNAL PROCESSING;

EID: 52549116515     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.1992.229988     Document Type: Conference Paper

References (15)

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