SCOPUS 정보 검색 플랫폼 - 논문 보기

메뉴 건너뛰기

Volumn 2, Issue 1-4, 1987, Pages 113-129

Global wire routing in two-dimensional arrays

(6) Karp, R M a Leighton, F T b Rivest, R L b Thompson, C D a Vazirani, U V a Vazirani, V V c

a UNIVERSITY OF CALIFORNIA (United States)

b MASSACHUSETTS INSTITUTE OF TECHNOLOGY (United States)

c Department of Obstetrics Gynecology (United States)

Author keywords

Computer aided design for integrated circuits; Gate arrays; Global routing; Integer programming; Linear programming

Indexed keywords

COMPUTER PROGRAMMING - ALGORITHMS; MATHEMATICAL PROGRAMMING, LINEAR;

GLOBAL WIRE ROUTING; INTEGER PROGRAMMING;

INTEGRATED CIRCUITS, VLSI;

EID: 52449148608 PISSN: 01784617 EISSN: 14320541 Source Type: Journal
DOI: 10.1007/BF01840353 Document Type: Article

Times cited : (25)

References (20)

1
- 0002060665
- “Integer-making” theorems
- (1981) Discrete Appl. Math. , vol.3 , pp. 1-8
- Beck, J.¹ Fiala, T.²

2
- 0021412333
- A framework for solving VLSI graph layout problems
- (1984) J. Comput. System Sci. , vol.28 , pp. 300-343
- Bhatt, S.N.¹ Leighton, F.T.²

3
- 0020828718
- Hierarchical wire routing
- (1983) IEEE Trans. Computer-Aided Design , vol.2 , pp. 223-234
- Burstein, M.¹ Pelavin, R.²

4
- 84936678883
- K. A. Chen, M. Feuer, K. H. Khokhani, N. Nan, and S. Schmidt, The chip layout problem: an automatic wiring procedure, Proceedings of the 14th Design Automation Conference, New Orleans, 1977, pp. 298–302.

5
- 84936678884
- P. Czerwinski and V. Ramachandran, Optimal VLSI graph embeddings in variable aspect ratio rectangles, Algorithmica (submitted).

6
- 0019530332
- Two-dimensional stochastic model for interconnections in master slice integrated circuit
- (1981) IEEE Trans. Circuits and Systems , vol.28 , pp. 127-138
- El Gamal, A.A.¹

7
- 0020497877
- Wire routing machines-new tools for VLSI physical design
- (1983) Proc. IEEE , vol.71 , pp. 57-65
- Hong, S.J.¹ Nair, R.²

8
- 0022132801
- A decomposition algorithm for circuit routing
- (1985) Math. Programming Stud. , vol.24 , pp. 87-103
- Hu, T.C.¹ Shing, M.T.²

9
- 49049144709
- The NP-completeness column: an outgoing guide
- (1982) J. Algorithms , vol.3 , pp. 381-395
- Johnson, D.S.¹

10
- 84936678896
- R. M. Karp, F. T. Leighton, R. L. Rivest, C. D. Thompson, U. Vazirani, and V. Vazirani, Global wire-routing in two-dimensional arrays, Proceedings of the 24th FOCS Conference, 1983, pp. 453–459.

11
- 84936678897
- M. R. Kramer and J. van Leeuwen, Wire-routing is NP-complete, Vakgroep Informatica Technical Report RUU-CS-82-4, Rijksuniversiteit Utrecht, 1982, 11 pp.

12
- 84936678894
- F. T. Leighton, New lower-bound techniques for VLSI, Proceedings 22nd FOCS Conference, 1981, pp. 1–12.

13
- 84936678895
- F. T. Leighton, A layout strategy for VLSI which is provably good, Proceedings of the 14th ACM STOC Conference, 1982, pp. 85–98.

14
- 84936678890
- C. E. Leiserson, Area-efficient graph layouts (for VLSI), Proceedings 21st FOCS Conference, 1980, pp. 270–281.

15
- 84936678891
- J. T. Li and M. Marek-Sadowska, Global routing for gate arrays, IEEE Trans. Computer-Aided Design, (1984), 298–308.

16
- 84936678888
- A. P.-C. Ng, P. Raghavan, and C. D. Thompson, Experimental results for a linear program global router, Proceedings of the 23rd ACM/IEEE Design Automation Conference, 1986, 659–662.

17
- 0021816808
- A linear-time routing algorithm for convex grids
- (1985) IEEE Trans. Computer-Aided Design , vol.4 , pp. 68-76
- Nishizeki, T.¹ Saito, N.² Suzuki, K.³

18
- 84936678889
- P. Raghavan and C. D. Thompson, Randomized rounding: a technique for provably good algorithms and algorithmic proofs, Combinatorica (to appear).

19
- 84936678892
- C. Thompson, “Area-time complexity for VLSI,”Proceedings of the 11th ACM STOC Conference, 1979, pp. 81–88.

20
- 0020833211
- Global wiring by simulated annealing
- (1983) IEEE Trans. Computer-Aided Design , vol.2 , pp. 215-222
- Vecchi, M.P.¹ Kirkpatrick, S.²

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.