A FPGA partial reconfiguration design approach for cognitive radio based on NoC architecture

2008 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA

Volumn , Issue , 2008, Pages 355-358

  Delorme, Julien ^a   Martin, Jérôme ^b   Nafkha, Amor ^a   Moy, Christophe ^a   Clermidy, Fabien ^b   Leray, Pierre ^a   Palicot, Jacques ^a  

^a IETR   (France)

^b CEA LETI   (France)

Author keywords

ASIC; FPGA; ICAP; NoC; Partial reconfiguration; SDR; SoC; Telecommunication

Indexed keywords

COMMUNICATION SYSTEMS; ELECTRIC NETWORK TOPOLOGY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INFORMATION RETRIEVAL; INTERNET PROTOCOLS; LOCAL AREA NETWORKS; STANDARDS; WIRELESS LOCAL AREA NETWORKS (WLAN); WIRELESS TELECOMMUNICATION SYSTEMS;

ASIC; COGNITIVE RADIO; COMMUNICATION DEVICES; COMMUNICATION MODULES; DESIGN APPROACHES; DIFFERENT SERVICES; FPGA; HARDWARE STRUCTURES; HARDWARE SYSTEMS; ICAP; IEEE 802.11 A/B/G; IP BLOCKS; NOC; NOC ARCHITECTURES; NOC DESIGN; PARTIAL RECONFIGURATION; RE CONFIGURABILITY; RECONFIGURABLE HARDWARE PLATFORM; RECONFIGURABLE RADIOS; SDR; SDR CONCEPT; SOC; SOFTWARE-DEFINED RADIOS; SOFTWARE-DEFINED-RADIO; TELECOMMUNICATION; USER DEMANDS; WIRELESS NETWORKS; WIRELESS-LAN;

RADIO COMMUNICATION;

EID: 52449120690     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NEWCAS.2008.4606394     Document Type: Conference Paper

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