Characterization and modeling of program/erase induced device degradation in 2T-FNFN-NOR flash memories

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Volumn , Issue , 2008, Pages

  Tao, Guoqiao ^a   Chauveau, Helene ^a   Boter, Dick ^a   Van Der Vegt, Erik ^a   Dormans, Do ^a   Verhaar, Rob ^a  

^a NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SOFTWARE; DATA STORAGE EQUIPMENT; DEGRADATION; ELECTRIC CURRENTS; ELECTRIC NETWORK ANALYSIS; ELECTRONICS INDUSTRY; ESTIMATION; FAILURE ANALYSIS; FLASH MEMORY; INTEGRATED CIRCUITS; QUALITY ASSURANCE; SAFETY FACTOR; SOFTWARE RELIABILITY; SULFATE MINERALS; TECHNICAL PRESENTATIONS;

AND MODELING; DEGRADATION MECHANISMS; DEVICE DEGRADATION; EXPERIMENTAL STUDIES; FOWLER-NORDHEIM TUNNELING; GENERATION PROCESS; INTERNATIONAL SYMPOSIUM; MEMORY ARRAYS; NOR FLASH; PRODUCT RELIABILITY; QUANTITATIVE MODELING; RELIABILITY PERFORMANCE; SOFTWARE TOOLS; STRESS CONDITIONS; TRANSISTOR ARRAYS;

RELIABILITY;

EID: 52149084555     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPFA.2008.4588191     Document Type: Conference Paper

References (8)

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4. G. Tao , et al., "A quantitative study of endurance characteristics and its temperature dependence of embedded Flash memories with 2T-FNFN NOR device architecture", In IEEE TDMR Vol 7, No. 2, (June 2007), pp 304 -309.
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7. N. Mielke, et.al. "Bit Error Rate in NAND Flash Memories", IEEE IRPS 2008, pp 9-19.
8. M. Vertregt, "The analog challenge of nanometer CMOS", IEDM 2006, pp 1-8