A 1.2V 30mW 8b 800MS/s time-interleaved ADC in 65nm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2008, Pages 72-73

  Tu, Wei Hsuan ^a   Kang, Tzung Hung ^a  

^a MEDIATEK INC   (Taiwan)

Author keywords

Low power; Time interleaved pipeline ADC

Indexed keywords

BUFFER AMPLIFIERS; PIPELINES; VLSI CIRCUITS;

65NM CMOS; ACTIVE AREA; CURRENT REUSING; DIGITAL CMOS; LOW POWER; REFERENCE VOLTAGES; TIME-INTERLEAVED ADC; TIME-INTERLEAVED PIPELINE ADC;

CMOS INTEGRATED CIRCUITS;

EID: 51949111925     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2008.4585956     Document Type: Conference Paper

References (2)

1. Kiyoshi Makigawa et al., "A 7bit 800Msps 120mW Folding and Interpolation ADC Using a Mixed-Averaging Scheme," Symp. VLSI Circuits Dig. of Tech. Papers, June 2007
2. Cheng-Chung Hsu et al. "A 7b 1.1GS/s Reconfigurable Time-Interleaved ADC in 90nm CMOS," Symp. VLSI Circuits Dig. of Tech. Papers, June 2007