A 0.4ps-RMS-jitter 1-3GHz ring-oscillator PLL using phase-noise preamplification

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2008, Pages 114-115

  Cao, Zhiheng ^a   Li, Yunchu ^b   Yan, Shouli ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b ANALOG DEVICES INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

JITTER; PHASE NOISE; VLSI CIRCUITS;

ANALOG TUNING; CHARGE PUMP CURRENTS; FULLY DIFFERENTIAL; IN-BAND NOISE; LOOP FILTER; PREAMPLIFICATION; REFERENCE SPUR; RING OSCILLATOR;

PHASE LOCKED LOOPS;

EID: 51949106411     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2008.4585973     Document Type: Conference Paper

References (5)

1. A. Maxim, "A -86dBc reference spurs 1-5GHz 0.13μm CMOS PLL using a dual-path sampled loop filter architecture," IEEE Symposium ON VLSI Circuits, pp. 248-251, June 2005.
2. N. D. Dalt et al., "A sub-ps jitter PLL for clock generaiion in 0.12μm digital CMOS," JSSC, pp. 1275, July 2003.
3. M. Kossel et al., "A Low-Jitter Wideband Multiphase PLL in 90nm SOI CMOS Technology," ISSCC Dig. Tech. Papaers, pp. 44, 2005.
4. M. Brownless et al, "A 0.5-GHz to 2.5-GHz PLL with Fully Differential Supply Regulated Tuning," JSSC, pp. 2720, Dec. 2006.
5. T. Toifl et al., "A 0.94-ps-RMS-jitter 0.016-mm2 2.5-GHz multiphase generator PLL wiih 360 degree digitally programmable phase shift for 10Gb/s serial links," JSSC, pp. 2700, Dec. 2005.