A TeraBit/s-throughput, SerDes-based interface for a third-generation 16 core 32 thread chip-multithreading SPARC processor

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2008, Pages 200-201

  Nasrullah, Jawad ^a   Amin, Arif ^a   Ahmad, Waseem ^a   Qin, Zuxu ^a   Mushtaq, Zahid ^a   Javed, Osman ^a   Yoon, Joon ^a   Chua, Leandro ^a   Huang, Dawei ^a   Huang, Baoqing ^a   Vichare, Makarand ^a   Ho, Kenneth ^a   Rashid, Mamun ^a  

^a SUN MICROSYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

POLYCHLORINATED BIPHENYLS; VLSI CIRCUITS;

CHIP MULTITHREADING; HALF-RATE; LINEAR EQUALIZATION; OUTPUT SWING; PROCESSOR INTERFACES; TERABIT; THIRD GENERATION;

MULTITASKING;

EID: 51949101925     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2008.4586006     Document Type: Conference Paper

References (6)

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2. D. C. Pham, et al., JSSC, vol. 41, no. 1, Jan 2006.
3. G. Konstadinidis, et al., in press, ISSCC 2008.
4. M. Sorna, et al., et al., ISSCC, pp. 62-63, Feb 2005.
5. R. Payne, et al., ISSCC, pp. 68-69, Feb 2005.
6. P. Landman, et al., ISSCC, pp. 66-67, Feb 2005.