An asynchronous power aware and adaptive NoC based circuit

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2008, Pages 190-191

  Beigne E ^a   Clermidy, F ^a   Durupt, J ^a   Lhermet, H ^a   Miermont, S ^a   Thonnart, Y ^a   Tran Xuan, T ^a   Valentian, A ^a   Varreau, D ^a   Vivet, P ^a  

^a CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER UTILIZATION; POWER MANAGEMENT; SERVERS; TIMING CIRCUITS; VLSI CIRCUITS;

ACTIVITY DETECTION; ADAPTIVE DESIGN TECHNIQUES; ASYNCHRONOUS NETWORKS; DYNAMIC POWER CONSUMPTION; GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS; POWER-AWARE; STATIC POWER CONSUMPTION;

NETWORK-ON-CHIP;

EID: 51949095898     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2008.4586002     Document Type: Conference Paper

References (3)

1. H. Kawaguchi, et al. "A Super Cut-Off CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage with Picoampere Standby Current," IEEE Journal of Solid-State Circuits, vol. 35, no. 10, pp.1498-1501, Oct. 2000
2. M. Weiser et al. "Scheduling for reduced CPU energy". In Operating Systems Design and Implementation, pp. 1323, April 1994.
3. A. Valentian et al. "Gate Bias Circuit for an SCCMOS Power Switch achieving maximum leakage reduction", ESSCIRC 2007, 11-13 September, Munich, Germany.