The Reduceron: Widening the von Neumann bottleneck for graph reduction using an FPGA

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 5083 LNCS, Issue , 2008, Pages 129-146

  Naylor, Matthew ^a   Runciman, Colin ^a  

^a UNIVERSITY OF YORK   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE EQUIPMENT; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LINGUISTICS; MICROCOMPUTERS;

BYTE CODES; FUNCTIONAL LANGUAGES; GRAPH REDUCTIONS; HASKELL; INTERNATIONAL SYMPOSIUM; NEUMANN; PROCESSOR SPEEDS; PROTOTYPE MACHINE;

GRAPH THEORY;

EID: 51849148341     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-85373-2_8     Document Type: Conference Paper

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