Stacked-chip implementation of on-chip buck converter for distributed power supply system in sips

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 11, 2007, Pages 2404-2410

  Onizuka, Kohei ^a   Inagaki, Kenichi ^a   Kawaguchi, Hiroshi ^b   Takamiya, Makoto ^a   Sakurai, Takayasu ^c  

^a INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

^b KOBE UNIVERSITY   (Japan)

^c UNIVERSITY OF TOKYO   (Japan)

Author keywords

Buck converter; Distributed power supply; stacked chip; System in a package (SiP)

Indexed keywords

ACTIVE PARTS; BUCK CONVERTER; CHIP IMPLEMENTATIONS; CHIP STACKING; DISTRIBUTED POWER SUPPLY; DISTRIBUTED POWER SUPPLY SYSTEMS; GLASS EPOXIES; MAXIMUM POWER; ON CHIPS; OUTPUT CURRENTS; OUTPUT FILTERS; STACKED CHIP; SYSTEM- IN-A-PACKAGE (SIP); VOLTAGE CONVERSION RATIOS;

ELECTRIC POWER DISTRIBUTION; ELECTRIC POWER TRANSMISSION NETWORKS; ELECTRIC POWER UTILIZATION; INTERNET PROTOCOLS; POWER TRANSMISSION;

ELECTRIC INVERTERS;

EID: 51849141567     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.906204     Document Type: Conference Paper

References (15)

1. The International Technology Roadmap for Semiconductors 2005 [Online]. Available: http://www.itrs.net/Common/2005ITRS/ Home2005.htm
2. P. Hazucha, G. Schrom, J.-H. Hahn, B. Bloechel, P. Hack, G. Dermer, S. Narendra, D. Gardner, T. Karnik, V. De, and S. Borker, "A 233- MHz, 80%-87% efficient four-phase DC-DC converter utilizing aircore inductors on package," IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 838-845, Apr. 2005.
3. S. Abedinpour, B. Bakkaloglu, and S. Kiaei, "A multi-stage interleaved synchronous buck converter with integrated output filter in a 0.18 -m SiGe process," in IEEE ISSCC Dig. Tech, Papers, 2006, pp. 356-357.
4. M. Alimadadi, S. Sheikhaei, G. Lemieux, S. Mirabbasi, and P. Palmer, "A 3 GHz switching DC-DC converter using clock-tree charge-recycling in 90 nm CMOS with integrated output filter," in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 532-5533.
5. G. Schrom, P. Hazucha, F. Paillet, D. S. Gardner, S. T. Moon, and T. Karnik, "Optimal design of monolithic integrated DC-DC converters," in Proc. IEEE Int. Conf. IC Design Technology, 2006, pp. 65-67.
6. T. Sakurai and R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 584-594, Feb. 1990.
7. G. Uvieghara, M.-C. Kuo, J. Arceo, J. Cheung, J. Lee, X. Niu, R. Sankuratri, M. Severson, O. Arias, Y. Chang, S. King, K.-C. Lai, Y. Tian, S. Varadarajan, J. Wang, K. Yen, L. Yuan, N. Chen, D. Hsu, D. Lisk, S. Khan, A. Fahim, C.-L. Wang, J. Dejaco, Z. Mansour, and M. Sani, "A highly-integrated 3G CDMA2000 1X cellular baseband chip with GSM/AMPS/GPS/Bluetooth/Multimedia capabilities and ZIF RF support," in IEEE ISSCC Dig. Tech. Papers, 2004, pp. 422-536.
8. S. S. Mohan, M. del Mar Hershenson, S. P. Boyd, and T. H. Lee, "Simple accurate expressions for planar spriral inductors," IEEE J. Solid-State Circuits, vol. 34, no. 10, pp. 1419-1424, Oct. 1999.
9. V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, "Efficiency analysis of a high frequency buck converter for on-chip integration with a dual-V microprocessor," in Proc. Eur. Solid-State Circuits Conf., Sep. 2002, pp. 743-746.
10. V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, "Monolithic DC-DC converter analysis and MOSFET gate voltage optimization," in Proc. 4th Int. Symp. Quality Electronic Design,Mar. 2003, pp. 279-284.
11. V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, "Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 3, pp. 514-522, Jun. 2003.
12. V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, "Lowvoltage- swing monolithic dc-dc conversion," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 51, no. 5, pp. 241-248, May 2004.
13. G. Schrom, P. Hazucha, J. Hahn, D. S. Gardner, B. A. Bloechel, G. Dermer, S. G. Narendra, T. Karnik, and V. De, "A 480-MHz, multiphase interleaved buck DC-DC converter with hysteretic control," in Proc. 35th Annu. IEEE Power Electronics Specialists Conf., Jun. 2004, pp. 4702-4707.
14. T. Ezaki, K. Kondo, H. Ozaki, N. Sasaki, H. Yonernura, M. Kitano, S. Tanaka, and T. Hirayarna, "A 160 Gb/s interface design configuration for multichip LSI," in IEEE ISSCC Dig. Tech. Papers, 2004, pp. 140-141.
15. G. Schrom, P. Hazucha, J.-H. Hahn, V. Kursun, D. Gardner, S. Narendra, T. Karnik, and V. De, "Feasibility of monolithic and 3D-stacked DC-DC converters for mircoprocessors in 90 nm technology generation," in Proc. ISLPED, 2004, pp. 263-268.