An architecture for exploiting multi-core processors to parallelize network intrusion prevention

2007 IEEE Sarnoff Symposium, SARNOFF

Volumn , Issue , 2007, Pages

  Paxson, Vern ^a   Sommer, Robin ^a   Weaver, Nicholas ^b  

^a LAWRENCE BERKELEY NATIONAL LABORATORY   (United States)

^b INTERNATIONAL COMPUTER SCIENCE INSTITUTE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONY; CACHE LOCALITY; COMMODITY HARDWARE; COMPLEX ANALYSIS; CONCURRENT EXECUTION; EVENT-BASED SYSTEMS; MOORE'S LAWS; MULTI-CORE ARCHITECTURE; MULTI-CORE PROCESSORS; NETWORK ATTACK ANALYSIS; NETWORK ATTACKS; NETWORK INTERFACES; NETWORK INTRUSIONS; NETWORK TRAFFICS; PARALLEL EXECUTIONS; PERFORMANCE GAINS; UNIPROCESSOR;

CHLORINE COMPOUNDS; COMPUTER CRIME; INTERNET; MICROPROCESSOR CHIPS; QUALITY ASSURANCE; RELIABILITY; WEIGHT CONTROL;

FAILURE ANALYSIS;

EID: 51849138756     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SARNOF.2007.4567341     Document Type: Conference Paper

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