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Volumn , Issue , 2008, Pages 286-291

Core allocation and relocation management for a self dynamically reconfigurable architecture

Author keywords

[No Author keywords available]

Indexed keywords

BITSTREAMS; COMPLETE SOLUTIONS; COMPLEX MANAGEMENT; DYNAMICAL RECONFIGURATION; DYNAMICALLY RECONFIGURABLE ARCHITECTURE; POWERFUL APPROACH; RECONFIGURABLE SYSTEMS; RECTANGULAR SHAPES; RUN-TIME; SELF-RECONFIGURATION; VALIDATION PHASE; VLSI TECHNOLOGIES;

EID: 51849095892     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2008.39     Document Type: Conference Paper
Times cited : (15)

References (14)
  • 2
    • 0033891806 scopus 로고    scopus 로고
    • Fast template placement for reconfigurable computing systems
    • pages
    • K. Bazargan, R. Kastner, and M. Sarrafzadeh. Fast template placement for reconfigurable computing systems. In IEEE Design and Test of Computers, Vol.17, Iss.1, pages:68-83, 2000.
    • (2000) IEEE Design and Test of Computers , vol.17 , Issue.ISS.1 , pp. 68-83
    • Bazargan, K.1    Kastner, R.2    Sarrafzadeh, M.3
  • 4
    • 34548780538 scopus 로고    scopus 로고
    • In-Circuit Partial Reconfiguration of RocketIO Attributes
    • Technical Report XAPP662, Xilinx Inc, January
    • V. Ech, P. Kalra, R. LeBlanc, and J. McManus. In-Circuit Partial Reconfiguration of RocketIO Attributes. Technical Report XAPP662, Xilinx Inc., January 2003.
    • (2003)
    • Ech, V.1    Kalra, P.2    LeBlanc, R.3    McManus, J.4
  • 5
    • 50049103264 scopus 로고    scopus 로고
    • F. Ferrandi, M. Morandi, M. Novati, M. D. Santambrogio, and D. Sciuto. Dynamic reconfiguration: Core relocation via partial bitstreams filtering with minimal overhead. In International Symposium on System-on-Chip 06, pages 33-26,.
    • F. Ferrandi, M. Morandi, M. Novati, M. D. Santambrogio, and D. Sciuto. Dynamic reconfiguration: Core relocation via partial bitstreams filtering with minimal overhead. In International Symposium on System-on-Chip 06, pages 33-26,.
  • 7
    • 0003740827 scopus 로고    scopus 로고
    • Washington University, Department of Computer Science, Technical Report WUCS-01-13
    • July
    • E. Horta and J. W. Lockwood. Parbit: A tool to transform bitfiles to implement partial reconfiguration of field programmable gate arrays (fpgas). Washington University, Department of Computer Science, Technical Report WUCS-01-13, July 2001.
    • (2001)
    • Horta, E.1    Lockwood, J.W.2
  • 8
    • 51849129855 scopus 로고    scopus 로고
    • X. Inc. Opb hwicap (v1.00.b) product specification. Technical report, Xilinx Inc., March 2005.
    • X. Inc. Opb hwicap (v1.00.b) product specification. Technical report, Xilinx Inc., March 2005.
  • 9
    • 51849115000 scopus 로고    scopus 로고
    • X. Inc. Virtex-II Pro and Virtex-II Pro X FPGA User Guide, 2005.
    • X. Inc. Virtex-II Pro and Virtex-II Pro X FPGA User Guide, 2005.
  • 10
    • 51849083304 scopus 로고    scopus 로고
    • X. Inc. Virtex-4 user guide. Technical Report ug70, Xilinx Inc., March 2007.
    • X. Inc. Virtex-4 user guide. Technical Report ug70, Xilinx Inc., March 2007.
  • 11
    • 51849096746 scopus 로고    scopus 로고
    • X. Inc. Virtex-5 user guide. Technical Report ug190, Xilinx Inc., February 2007.
    • X. Inc. Virtex-5 user guide. Technical Report ug190, Xilinx Inc., February 2007.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.