Fast multivariate signature generation in hardware: The case of rainbow

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 2008, Pages 25-30

  Balasubramanian, Sundar ^a   Carter, Harold W ^a   Bogdanov, Andrey ^b   Rupp, Andy ^b   Ding, Jintai ^a  

^a UNIVERSITY OF CINCINNATI   (United States)

^b RUHR UNIVERSITY BOCHUM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION-SPECIFIC SYSTEMS; GAUSSIAN ELIMINATION; INTERNATIONAL CONFERENCES;

ARSENIC COMPOUNDS;

EID: 51649129071     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2008.4580149     Document Type: Conference Paper

References (13)

1. J. Ding and D. Schmidt, "Rainbow, a new Multivariable Polynomial Signature Scheme," in Proc. of ACNS'05, 2005.
2. A. Kipnis, J. Patarin, and L. Goubin, "Unbalanced Oil and Vinegar signature schemes," in Proc. of EUROCRYPT'99, 1999.
3. A. Bodganov, M. Mertens, C. Paar, J. Pelzl, and A. Rupp, "A Parallel Hardware Architecture for fast Gaussian Elimination over GF(2)." in Proc. of FCCM'06, 2006.
4. B.-Y. Yang, C.-M. Cheng, B.-R. Chen, and J.-M. Chen, "Implementing Minimized Multivariate PKC on Low-Resource Embedded Systems," in SPC'06, 2006.
5. O. Billet and H. Gilbert, "Cryptanalysis of Rainbow," in Proc. of SCN'06, 2006.
6. L. H. J. Ding, B. Yang and J. Chen, "Notes on Design Criteria for Rainbow-Type Multivariates," IACR eprint report 2006/307, 2006.
7. B.-Y. Yang and J. Ding, "New Differential Attacks on Rainbow-like Multivariate Signature Schemes and Improved Designs," Preprint, University of Cincinnati, 2007.
8. C. Paar, "Efficient VLSI architectures for bit-parallel computation in Galois Fields," Ph.D. dissertation, Institute of Expermiental Mathematics, University of Essen, Germany, 1994.
9. C. Paar and M. Rosner, "Comparison of Arithmetic Architectures for Reed-Solomon decoders in reconfigurable hardware," in Proc. of FCCM '97, 1997.
10. J. Großschädl, "High-Speed RSA Hardware Based on Barret's Modular Reduction Method," in Proc. of CHES'00, 2000.
11. A. Satoh and K. Takano, "A scalable dual-field elliptic curve cryptographic processor," IEEE TC, 2003.
12. R. Schroeppel, C. Beaver, R. Gonzales, R. Miller, and T. Draelos, "A Low-Power Design of an Elliptic Curve Digital Signature Chip," in Proc. of CHES'02, 2002.
13. B.-Y. Yang and J.-M. Chen, "Building secure tame-like multivariate public-key cryptosystems: The new TTS," in Proc. of ACISP'05, 2005.