A hardware framework for the fast generation of multiple ong-period random number streams

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2008, Pages 245-254

  Dalal, Ishaan L ^a   Stefan, Deian ^a  

^a Cooper Union ^*  (United States)

Author keywords

FPGA; Mersenne twister; Parallelized architecture; Random number generator

Indexed keywords

ARCHITECTURAL FEATURES; FPGA; FPGA IMPLEMENTATIONS; HARDWARE FRAMEWORK; HARDWARE IMPLEMENTATIONS; HIGH QUALITY; LINEAR RECURRENCES; MERSENNE TWISTER; MERSENNE TWISTERS; MONTE CARLO; MULTIPLE STREAMS; NORMAL RANDOM VARIABLE; PARALLEL FRAMEWORK; PARALLELIZED ARCHITECTURE; PROGRAMMABLE LOGIC; PSEUDO RANDOM NUMBER GENERATORS; PSEUDORANDOM SEQUENCES; RANDOM NUMBER GENERATOR; RANDOM NUMBER GENERATORS; RANDOM NUMBERS; REAL-WORLD APPLICATION; SCIENTIFIC APPLICATIONS; SCIENTIFIC SIMULATIONS; SOFTWARE IMPLEMENTATION; STOCHASTIC SIMULATIONS; SUB-STREAMS; TESTU01; TRANSPORT SIMULATION;

COMPUTER HARDWARE DESCRIPTION LANGUAGES; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; LOGIC GATES; NUMBER THEORY; PARALLEL ALGORITHMS; RANDOM PROCESSES; RANDOM VARIABLES; STATISTICAL TESTS; STOCHASTIC MODELS;

RANDOM NUMBER GENERATION;

EID: 51649090250     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1344671.1344707     Document Type: Conference Paper

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